We need proper scheduling for 4-src ops to work, so for now disable
condition fusing so we cap at 3-src at a performance penalty. A bit of a
hack but I'd rather not build hacks into a scheduler that will be
rewritten soon anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
alu.src[1] = BIR_INDEX_ZERO;
alu.src_types[1] = alu.src_types[0];
+ /* TODO: Reenable cond fusing when we can split up registers
+ * when scheduling */
+#if 0
bi_fuse_csel_cond(&alu, instr->src[0],
&constants_left, &constant_shift, comps);
+#endif
} else if (alu.type == BI_BITWISE) {
/* Implicit shift argument... at some point we should fold */
alu.src[2] = BIR_INDEX_ZERO;