Fixes so that it compiles properly. Still working on .py file issues.
authorRon Dreslinski <rdreslin@umich.edu>
Mon, 27 Feb 2006 21:33:11 +0000 (16:33 -0500)
committerRon Dreslinski <rdreslin@umich.edu>
Mon, 27 Feb 2006 21:33:11 +0000 (16:33 -0500)
SConscript:
    Add Back memory to be built
mem/physical.hh:
    Fix function declerations
python/m5/objects/BaseCPU.py:
    Remove IL1 and DL1 params from the cpu object

--HG--
extra : convert_revision : 2f285dc626bc8d84d095def68e986fe7e6f3d8e9

SConscript
mem/physical.hh
python/m5/objects/BaseCPU.py

index 078b1e831360c636743a810885ce3e8f3c98baa0..1c13a930762a95118d290f49a1dbce9ad8436d03 100644 (file)
@@ -91,6 +91,7 @@ base_sources = Split('''
        cpu/static_inst.cc
         cpu/sampler/sampler.cc
 
+        mem/memory.cc
         mem/page_table.cc
         mem/physical.cc
         mem/port.cc
index fb2d0d74342a5cb243d611b96c3a03a05c70c518..90515d7d1c90fbc2f3eae458124088c825f58136 100644 (file)
@@ -70,9 +70,9 @@ class PhysicalMemory : public Memory
 
     std::map<std::string, MemoryPort*> memoryPortList;
 
-    Port * PhysicalMemory::getPort(const char *if_name);
+    virtual Port * getPort(const char *if_name);
 
-    Port * addPort(std::string portName);
+    virtual Port * addPort(std::string portName);
 
     int numPorts;
 
index fac452285d8e842083a52434da8fab0a7d335bd7..e5e43022f3645711850ac5dfc88a2323d3bc88da 100644 (file)
@@ -2,8 +2,6 @@ from m5 import *
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
-    icache = Param.BaseMem(NULL, "L1 instruction cache object")
-    dcache = Param.BaseMem(NULL, "L1 data cache object")
 
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")