SConscript:
Add Back memory to be built
mem/physical.hh:
Fix function declerations
python/m5/objects/BaseCPU.py:
Remove IL1 and DL1 params from the cpu object
--HG--
extra : convert_revision :
2f285dc626bc8d84d095def68e986fe7e6f3d8e9
cpu/static_inst.cc
cpu/sampler/sampler.cc
+ mem/memory.cc
mem/page_table.cc
mem/physical.cc
mem/port.cc
std::map<std::string, MemoryPort*> memoryPortList;
- Port * PhysicalMemory::getPort(const char *if_name);
+ virtual Port * getPort(const char *if_name);
- Port * addPort(std::string portName);
+ virtual Port * addPort(std::string portName);
int numPorts;
class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
- icache = Param.BaseMem(NULL, "L1 instruction cache object")
- dcache = Param.BaseMem(NULL, "L1 data cache object")
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB("Data TLB")