Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine

diff --cc techlibs/xilinx/synth_xilinx.cc
index ba9efc658cd7e89fc26155530c2a3c61889e15ee,c4c27d816562f621ca4456a8350a4a9ea9ffd7b7..dbafec301a133af639c85c509f80d077103e96cb
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -264,81 -204,79 +204,73 @@@ struct SynthXilinxPass : public ScriptP
                        }
                }
  
-               if (check_label(active, run_from, run_to, "fine"))
-               {
-                       if (!nosrl) {
-                               // shregmap -tech xilinx can cope with $shiftx and $mux
-                               //   cells for identifiying variable-length shift registers,
-                               //   so attempt to convert $pmux-es to the former
-                               Pass::call(design, "pmux2shiftx");
-                       }
+               if (check_label("fine")) {
+                       run("opt -fast");
+                       run("memory_map");
+                       run("dffsr2dff");
+                       run("dff2dffe");
  
-                       Pass::call(design, "opt -fast -full");
-                       Pass::call(design, "memory_map");
-                       Pass::call(design, "dffsr2dff");
-                       Pass::call(design, "dff2dffe");
++                      // shregmap -tech xilinx can cope with $shiftx and $mux
++                      //   cells for identifiying variable-length shift registers,
++                      //   so attempt to convert $pmux-es to the former
++                      if (!nosrl || help_mode)
++                              run("pmux2shiftx", "(skip if '-nosrl')");
 +
-                       if (vpr) {
-                               Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
-                       } else {
-                               Pass::call(design, "techmap -map +/xilinx/arith_map.v");
-                       }
++                      run("opt -full");
 +
-                       Pass::call(design, "opt -full");
+                       if (!vpr || help_mode)
+                               run("techmap -map +/xilinx/arith_map.v");
+                       else
+                               run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
  
-                       if (!nosrl) {
 -                      run("hierarchy -check");
 -                      run("opt -fast");
 -              }
 -
 -              if (check_label("map_cells"))
 -              {
+                       if (!nosrl || help_mode) {
                                // shregmap operates on bit-level flops, not word-level,
                                //   so break those down here
-                               Pass::call(design, "simplemap t:$dff t:$dffe");
-                               Pass::call(design, "show -format pdf -prefix show *depth=3*");
+                               run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
 -                              // shregmap -tech xilinx can cope with $shiftx and $mux
 -                              //   cells for identifiying variable-length shift registers,
 -                              //   so attempt to convert $pmux-es to the former
 -                              run("pmux2shiftx", "(skip if '-nosrl')");
 -                              // pmux2shiftx can leave behind a $pmux with a single entry
 -                              //   -- need this to clean that up before shregmap
 -                              run("opt_expr -mux_undef", "(skip if '-nosrl')");
                                // shregmap with '-tech xilinx' infers variable length shift regs
-                               Pass::call(design, "shregmap -tech xilinx -minlen 3");
-                               Pass::call(design, "opt -fast");
+                               run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
                        }
  
-                       Pass::call(design, "techmap");
-                       Pass::call(design, "opt -fast");
 -                      run("techmap -map +/xilinx/cells_map.v");
++                      run("techmap");
++                      run("opt -fast");
 +              }
 +
-               if (check_label(active, run_from, run_to, "map_cells"))
-               {
-                       Pass::call(design, "techmap -map +/xilinx/cells_map.v");
-                       Pass::call(design, "clean");
++              if (check_label("map_cells")) {
++                      run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+                       run("clean");
                }
  
-               if (check_label(active, run_from, run_to, "map_luts"))
 -              if (check_label("map_luts"))
--              {
-                       Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
-                       Pass::call(design, "clean");
 -                      run("opt -full");
 -                      run("techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
++              if (check_label("map_luts")) {
+                       if (help_mode)
+                               run("abc -luts 2:2,3,6:5,10,20 [-dff]");
+                       else
+                               run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+                       run("clean");
                        // This shregmap call infers fixed length shift registers after abc
                        //   has performed any necessary retiming
-                       if (!nosrl)
-                               Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
-                       Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
-                       Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+                       if (!nosrl || help_mode)
+                               run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+                       run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
+                       run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
                                        "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
-                       Pass::call(design, "clean");
+                       run("clean");
                }
  
-               if (check_label(active, run_from, run_to, "check"))
 -              if (check_label("check"))
--              {
-                       Pass::call(design, "hierarchy -check");
-                       Pass::call(design, "stat");
-                       Pass::call(design, "check -noinit");
++              if (check_label("check")) {
+                       run("hierarchy -check");
+                       run("stat");
+                       run("check -noinit");
                }
  
-               if (check_label(active, run_from, run_to, "edif"))
-               {
-                       if (!edif_file.empty())
-                               Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
-               }
-               if (check_label(active, run_from, run_to, "blif"))
 -              if (check_label("edif"))
--              {
-                       if (!blif_file.empty())
-                               Pass::call(design, stringf("write_blif %s", edif_file.c_str()));
++              if (check_label("edif")) {
+                       if (!edif_file.empty() || help_mode)
+                               run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
                }
  
-               log_pop();
 -              if (check_label("blif"))
 -              {
++              if (check_label("blif")) {
+                       if (!blif_file.empty() || help_mode)
+                               run(stringf("write_blif %s", edif_file.c_str()));
+               }
        }
  } SynthXilinxPass;