fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index b26689d50f5b7707df853f587c32a28412c5180d..1c4d6082b2361786b51b240b8a1d90f1ff9a8a5c 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -279,11 +279,13 @@ def _printinit(f, ios, ns):
                r += "end\n\n"
        return r
 
-def convert(f, ios=set(), name="top",
+def convert(f, ios=None, name="top",
   clock_domains=None,
   return_ns=False,
   memory_handler=verilog_mem_behavioral.handler,
   display_run=False):
+       if ios is None:
+               ios = set()
        if clock_domains is None:
                clock_domains = dict()
                for d in f.get_clock_domains():