if options.cpu_type == "O3_ARM_v7a_3":
try:
- from O3_ARM_v7a import *
+ from cores.arm.O3_ARM_v7a import *
except:
- print "arm_detailed is unavailable. Did you compile the O3 model?"
+ print "O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?"
sys.exit(1)
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
# The ARM detailed CPU is special in the sense that it doesn't exist
# in the normal object hierarchy, so we have to add it manually.
try:
- from O3_ARM_v7a import O3_ARM_v7a_3
+ from cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
_cpu_classes["O3_ARM_v7a_3"] = O3_ARM_v7a_3
except:
pass
# The calibrated ex5-model cores
try:
- from ex5_LITTLE import ex5_LITTLE
+ from cores.arm.ex5_LITTLE import ex5_LITTLE
_cpu_classes["ex5_LITTLE"] = ex5_LITTLE
except:
- pass
+ pass
try:
- from ex5_big import ex5_big
+ from cores.arm.ex5_big import ex5_big
_cpu_classes["ex5_big"] = ex5_big
except:
- pass
+ pass
# Add all CPUs in the object hierarchy.
+++ /dev/null
-# Copyright (c) 2012 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ron Dreslinski
-
-
-from m5.objects import *
-
-# Simple ALU Instructions have a latency of 1
-class O3_ARM_v7a_Simple_Int(FUDesc):
- opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
- count = 2
-
-# Complex ALU instructions have a variable latencies
-class O3_ARM_v7a_Complex_Int(FUDesc):
- opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
- OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
- OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
- count = 1
-
-
-# Floating point and SIMD instructions
-class O3_ARM_v7a_FP(FUDesc):
- opList = [ OpDesc(opClass='SimdAdd', opLat=4),
- OpDesc(opClass='SimdAddAcc', opLat=4),
- OpDesc(opClass='SimdAlu', opLat=4),
- OpDesc(opClass='SimdCmp', opLat=4),
- OpDesc(opClass='SimdCvt', opLat=3),
- OpDesc(opClass='SimdMisc', opLat=3),
- OpDesc(opClass='SimdMult',opLat=5),
- OpDesc(opClass='SimdMultAcc',opLat=5),
- OpDesc(opClass='SimdShift',opLat=3),
- OpDesc(opClass='SimdShiftAcc', opLat=3),
- OpDesc(opClass='SimdSqrt', opLat=9),
- OpDesc(opClass='SimdFloatAdd',opLat=5),
- OpDesc(opClass='SimdFloatAlu',opLat=5),
- OpDesc(opClass='SimdFloatCmp', opLat=3),
- OpDesc(opClass='SimdFloatCvt', opLat=3),
- OpDesc(opClass='SimdFloatDiv', opLat=3),
- OpDesc(opClass='SimdFloatMisc', opLat=3),
- OpDesc(opClass='SimdFloatMult', opLat=3),
- OpDesc(opClass='SimdFloatMultAcc',opLat=5),
- OpDesc(opClass='SimdFloatSqrt', opLat=9),
- OpDesc(opClass='FloatAdd', opLat=5),
- OpDesc(opClass='FloatCmp', opLat=5),
- OpDesc(opClass='FloatCvt', opLat=5),
- OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
- OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
- OpDesc(opClass='FloatMult', opLat=4),
- OpDesc(opClass='FloatMultAcc', opLat=5),
- OpDesc(opClass='FloatMisc', opLat=3) ]
- count = 2
-
-
-# Load/Store Units
-class O3_ARM_v7a_Load(FUDesc):
- opList = [ OpDesc(opClass='MemRead',opLat=2),
- OpDesc(opClass='FloatMemRead',opLat=2) ]
- count = 1
-
-class O3_ARM_v7a_Store(FUDesc):
- opList = [ OpDesc(opClass='MemWrite',opLat=2),
- OpDesc(opClass='FloatMemWrite',opLat=2) ]
- count = 1
-
-# Functional Units for this CPU
-class O3_ARM_v7a_FUP(FUPool):
- FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
- O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
-
-# Bi-Mode Branch Predictor
-class O3_ARM_v7a_BP(BiModeBP):
- globalPredictorSize = 8192
- globalCtrBits = 2
- choicePredictorSize = 8192
- choiceCtrBits = 2
- BTBEntries = 2048
- BTBTagSize = 18
- RASSize = 16
- instShiftAmt = 2
-
-class O3_ARM_v7a_3(DerivO3CPU):
- LQEntries = 16
- SQEntries = 16
- LSQDepCheckShift = 0
- LFSTSize = 1024
- SSITSize = 1024
- decodeToFetchDelay = 1
- renameToFetchDelay = 1
- iewToFetchDelay = 1
- commitToFetchDelay = 1
- renameToDecodeDelay = 1
- iewToDecodeDelay = 1
- commitToDecodeDelay = 1
- iewToRenameDelay = 1
- commitToRenameDelay = 1
- commitToIEWDelay = 1
- fetchWidth = 3
- fetchBufferSize = 16
- fetchToDecodeDelay = 3
- decodeWidth = 3
- decodeToRenameDelay = 2
- renameWidth = 3
- renameToIEWDelay = 1
- issueToExecuteDelay = 1
- dispatchWidth = 6
- issueWidth = 8
- wbWidth = 8
- fuPool = O3_ARM_v7a_FUP()
- iewToCommitDelay = 1
- renameToROBDelay = 1
- commitWidth = 8
- squashWidth = 8
- trapLatency = 13
- backComSize = 5
- forwardComSize = 5
- numPhysIntRegs = 128
- numPhysFloatRegs = 192
- numIQEntries = 32
- numROBEntries = 40
-
- switched_out = False
- branchPred = O3_ARM_v7a_BP()
-
-# Instruction Cache
-class O3_ARM_v7a_ICache(Cache):
- tag_latency = 1
- data_latency = 1
- response_latency = 1
- mshrs = 2
- tgts_per_mshr = 8
- size = '32kB'
- assoc = 2
- is_read_only = True
- # Writeback clean lines as well
- writeback_clean = True
-
-# Data Cache
-class O3_ARM_v7a_DCache(Cache):
- tag_latency = 2
- data_latency = 2
- response_latency = 2
- mshrs = 6
- tgts_per_mshr = 8
- size = '32kB'
- assoc = 2
- write_buffers = 16
- # Consider the L2 a victim cache also for clean lines
- writeback_clean = True
-
-# TLB Cache
-# Use a cache as a L2 TLB
-class O3_ARM_v7aWalkCache(Cache):
- tag_latency = 4
- data_latency = 4
- response_latency = 4
- mshrs = 6
- tgts_per_mshr = 8
- size = '1kB'
- assoc = 8
- write_buffers = 16
- is_read_only = True
- # Writeback clean lines as well
- writeback_clean = True
-
-# L2 Cache
-class O3_ARM_v7aL2(Cache):
- tag_latency = 12
- data_latency = 12
- response_latency = 12
- mshrs = 16
- tgts_per_mshr = 8
- size = '1MB'
- assoc = 16
- write_buffers = 8
- prefetch_on_access = True
- clusivity = 'mostly_excl'
- # Simple stride prefetcher
- prefetcher = StridePrefetcher(degree=8, latency = 1)
- tags = RandomRepl()
--- /dev/null
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
--- /dev/null
+# Copyright (c) 2012 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+
+from m5.objects import *
+
+# Simple ALU Instructions have a latency of 1
+class O3_ARM_v7a_Simple_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
+ count = 2
+
+# Complex ALU instructions have a variable latencies
+class O3_ARM_v7a_Complex_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
+ OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
+ OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
+ count = 1
+
+
+# Floating point and SIMD instructions
+class O3_ARM_v7a_FP(FUDesc):
+ opList = [ OpDesc(opClass='SimdAdd', opLat=4),
+ OpDesc(opClass='SimdAddAcc', opLat=4),
+ OpDesc(opClass='SimdAlu', opLat=4),
+ OpDesc(opClass='SimdCmp', opLat=4),
+ OpDesc(opClass='SimdCvt', opLat=3),
+ OpDesc(opClass='SimdMisc', opLat=3),
+ OpDesc(opClass='SimdMult',opLat=5),
+ OpDesc(opClass='SimdMultAcc',opLat=5),
+ OpDesc(opClass='SimdShift',opLat=3),
+ OpDesc(opClass='SimdShiftAcc', opLat=3),
+ OpDesc(opClass='SimdSqrt', opLat=9),
+ OpDesc(opClass='SimdFloatAdd',opLat=5),
+ OpDesc(opClass='SimdFloatAlu',opLat=5),
+ OpDesc(opClass='SimdFloatCmp', opLat=3),
+ OpDesc(opClass='SimdFloatCvt', opLat=3),
+ OpDesc(opClass='SimdFloatDiv', opLat=3),
+ OpDesc(opClass='SimdFloatMisc', opLat=3),
+ OpDesc(opClass='SimdFloatMult', opLat=3),
+ OpDesc(opClass='SimdFloatMultAcc',opLat=5),
+ OpDesc(opClass='SimdFloatSqrt', opLat=9),
+ OpDesc(opClass='FloatAdd', opLat=5),
+ OpDesc(opClass='FloatCmp', opLat=5),
+ OpDesc(opClass='FloatCvt', opLat=5),
+ OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
+ OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
+ OpDesc(opClass='FloatMult', opLat=4),
+ OpDesc(opClass='FloatMultAcc', opLat=5),
+ OpDesc(opClass='FloatMisc', opLat=3) ]
+ count = 2
+
+
+# Load/Store Units
+class O3_ARM_v7a_Load(FUDesc):
+ opList = [ OpDesc(opClass='MemRead',opLat=2),
+ OpDesc(opClass='FloatMemRead',opLat=2) ]
+ count = 1
+
+class O3_ARM_v7a_Store(FUDesc):
+ opList = [ OpDesc(opClass='MemWrite',opLat=2),
+ OpDesc(opClass='FloatMemWrite',opLat=2) ]
+ count = 1
+
+# Functional Units for this CPU
+class O3_ARM_v7a_FUP(FUPool):
+ FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
+ O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
+
+# Bi-Mode Branch Predictor
+class O3_ARM_v7a_BP(BiModeBP):
+ globalPredictorSize = 8192
+ globalCtrBits = 2
+ choicePredictorSize = 8192
+ choiceCtrBits = 2
+ BTBEntries = 2048
+ BTBTagSize = 18
+ RASSize = 16
+ instShiftAmt = 2
+
+class O3_ARM_v7a_3(DerivO3CPU):
+ LQEntries = 16
+ SQEntries = 16
+ LSQDepCheckShift = 0
+ LFSTSize = 1024
+ SSITSize = 1024
+ decodeToFetchDelay = 1
+ renameToFetchDelay = 1
+ iewToFetchDelay = 1
+ commitToFetchDelay = 1
+ renameToDecodeDelay = 1
+ iewToDecodeDelay = 1
+ commitToDecodeDelay = 1
+ iewToRenameDelay = 1
+ commitToRenameDelay = 1
+ commitToIEWDelay = 1
+ fetchWidth = 3
+ fetchBufferSize = 16
+ fetchToDecodeDelay = 3
+ decodeWidth = 3
+ decodeToRenameDelay = 2
+ renameWidth = 3
+ renameToIEWDelay = 1
+ issueToExecuteDelay = 1
+ dispatchWidth = 6
+ issueWidth = 8
+ wbWidth = 8
+ fuPool = O3_ARM_v7a_FUP()
+ iewToCommitDelay = 1
+ renameToROBDelay = 1
+ commitWidth = 8
+ squashWidth = 8
+ trapLatency = 13
+ backComSize = 5
+ forwardComSize = 5
+ numPhysIntRegs = 128
+ numPhysFloatRegs = 192
+ numIQEntries = 32
+ numROBEntries = 40
+
+ switched_out = False
+ branchPred = O3_ARM_v7a_BP()
+
+# Instruction Cache
+class O3_ARM_v7a_ICache(Cache):
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 2
+ tgts_per_mshr = 8
+ size = '32kB'
+ assoc = 2
+ is_read_only = True
+ # Writeback clean lines as well
+ writeback_clean = True
+
+# Data Cache
+class O3_ARM_v7a_DCache(Cache):
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 2
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '32kB'
+ assoc = 2
+ write_buffers = 16
+ # Consider the L2 a victim cache also for clean lines
+ writeback_clean = True
+
+# TLB Cache
+# Use a cache as a L2 TLB
+class O3_ARM_v7aWalkCache(Cache):
+ tag_latency = 4
+ data_latency = 4
+ response_latency = 4
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '1kB'
+ assoc = 8
+ write_buffers = 16
+ is_read_only = True
+ # Writeback clean lines as well
+ writeback_clean = True
+
+# L2 Cache
+class O3_ARM_v7aL2(Cache):
+ tag_latency = 12
+ data_latency = 12
+ response_latency = 12
+ mshrs = 16
+ tgts_per_mshr = 8
+ size = '1MB'
+ assoc = 16
+ write_buffers = 8
+ prefetch_on_access = True
+ clusivity = 'mostly_excl'
+ # Simple stride prefetcher
+ prefetcher = StridePrefetcher(degree=8, latency = 1)
+ tags = RandomRepl()
--- /dev/null
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
--- /dev/null
+# Copyright (c) 2012 The Regents of The University of Michigan
+# Copyright (c) 2016 Centre National de la Recherche Scientifique
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+# Anastasiia Butko
+# Louisa Bessad
+
+from m5.objects import *
+
+#-----------------------------------------------------------------------
+# ex5 LITTLE core (based on the ARM Cortex-A7)
+#-----------------------------------------------------------------------
+
+# Simple ALU Instructions have a latency of 3
+class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
+ opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
+
+# Complex ALU instructions have a variable latencies
+class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
+ opList = [ OpDesc(opClass='IntMult', opLat=7) ]
+
+class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
+ opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
+
+# Floating point and SIMD instructions
+class ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
+ opList = [ OpDesc(opClass='SimdAdd', opLat=6),
+ OpDesc(opClass='SimdAddAcc', opLat=4),
+ OpDesc(opClass='SimdAlu', opLat=4),
+ OpDesc(opClass='SimdCmp', opLat=1),
+ OpDesc(opClass='SimdCvt', opLat=3),
+ OpDesc(opClass='SimdMisc', opLat=3),
+ OpDesc(opClass='SimdMult',opLat=4),
+ OpDesc(opClass='SimdMultAcc',opLat=5),
+ OpDesc(opClass='SimdShift',opLat=3),
+ OpDesc(opClass='SimdShiftAcc', opLat=3),
+ OpDesc(opClass='SimdSqrt', opLat=9),
+ OpDesc(opClass='SimdFloatAdd',opLat=8),
+ OpDesc(opClass='SimdFloatAlu',opLat=6),
+ OpDesc(opClass='SimdFloatCmp', opLat=6),
+ OpDesc(opClass='SimdFloatCvt', opLat=6),
+ OpDesc(opClass='SimdFloatDiv', opLat=20, pipelined=False),
+ OpDesc(opClass='SimdFloatMisc', opLat=6),
+ OpDesc(opClass='SimdFloatMult', opLat=15),
+ OpDesc(opClass='SimdFloatMultAcc',opLat=6),
+ OpDesc(opClass='SimdFloatSqrt', opLat=17),
+ OpDesc(opClass='FloatAdd', opLat=8),
+ OpDesc(opClass='FloatCmp', opLat=6),
+ OpDesc(opClass='FloatCvt', opLat=6),
+ OpDesc(opClass='FloatDiv', opLat=15, pipelined=False),
+ OpDesc(opClass='FloatSqrt', opLat=33),
+ OpDesc(opClass='FloatMult', opLat=6) ]
+
+# Load/Store Units
+class ex5_LITTLE_MemFU(MinorDefaultMemFU):
+ opList = [ OpDesc(opClass='MemRead',opLat=1),
+ OpDesc(opClass='MemWrite',opLat=1) ]
+
+# Misc Unit
+class ex5_LITTLE_MiscFU(MinorDefaultMiscFU):
+ opList = [ OpDesc(opClass='IprAccess',opLat=1),
+ OpDesc(opClass='InstPrefetch',opLat=1) ]
+
+# Functional Units for this CPU
+class ex5_LITTLE_FUP(MinorFUPool):
+ funcUnits = [ex5_LITTLE_Simple_Int(), ex5_LITTLE_Simple_Int(),
+ ex5_LITTLE_Complex_IntMul(), ex5_LITTLE_Complex_IntDiv(),
+ ex5_LITTLE_FP(), ex5_LITTLE_MemFU(),
+ ex5_LITTLE_MiscFU()]
+
+class ex5_LITTLE(MinorCPU):
+ executeFuncUnits = ex5_LITTLE_FUP()
+
+class L1Cache(Cache):
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 2
+ tgts_per_mshr = 8
+ # Consider the L2 a victim cache also for clean lines
+ writeback_clean = True
+
+class L1I(L1Cache):
+ mshrs = 2
+ size = '32kB'
+ assoc = 2
+ is_read_only = True
+ tgts_per_mshr = 20
+
+class L1D(L1Cache):
+ mshrs = 4
+ size = '32kB'
+ assoc = 4
+ write_buffers = 4
+
+# TLB Cache
+# Use a cache as a L2 TLB
+class WalkCache(Cache):
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 2
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '1kB'
+ assoc = 2
+ write_buffers = 16
+ is_read_only = True
+ # Writeback clean lines as well
+ writeback_clean = True
+
+# L2 Cache
+class L2(Cache):
+ tag_latency = 9
+ data_latency = 9
+ response_latency = 9
+ mshrs = 8
+ tgts_per_mshr = 12
+ size = '512kB'
+ assoc = 8
+ write_buffers = 16
+ prefetch_on_access = True
+ clusivity = 'mostly_excl'
+ # Simple stride prefetcher
+ prefetcher = StridePrefetcher(degree=1, latency = 1)
+ tags = RandomRepl()
+
+
--- /dev/null
+# Copyright (c) 2012 The Regents of The University of Michigan
+# Copyright (c) 2016 Centre National de la Recherche Scientifique
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+# Anastasiia Butko
+# Louisa Bessad
+
+from m5.objects import *
+
+#-----------------------------------------------------------------------
+# ex5 big core (based on the ARM Cortex-A15)
+#-----------------------------------------------------------------------
+
+# Simple ALU Instructions have a latency of 1
+class ex5_big_Simple_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
+ count = 2
+
+# Complex ALU instructions have a variable latencies
+class ex5_big_Complex_Int(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True),
+ OpDesc(opClass='IntDiv', opLat=11, pipelined=False),
+ OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
+ count = 1
+
+# Floating point and SIMD instructions
+class ex5_big_FP(FUDesc):
+ opList = [ OpDesc(opClass='SimdAdd', opLat=3),
+ OpDesc(opClass='SimdAddAcc', opLat=4),
+ OpDesc(opClass='SimdAlu', opLat=4),
+ OpDesc(opClass='SimdCmp', opLat=4),
+ OpDesc(opClass='SimdCvt', opLat=3),
+ OpDesc(opClass='SimdMisc', opLat=3),
+ OpDesc(opClass='SimdMult',opLat=6),
+ OpDesc(opClass='SimdMultAcc',opLat=5),
+ OpDesc(opClass='SimdShift',opLat=3),
+ OpDesc(opClass='SimdShiftAcc', opLat=3),
+ OpDesc(opClass='SimdSqrt', opLat=9),
+ OpDesc(opClass='SimdFloatAdd',opLat=6),
+ OpDesc(opClass='SimdFloatAlu',opLat=5),
+ OpDesc(opClass='SimdFloatCmp', opLat=3),
+ OpDesc(opClass='SimdFloatCvt', opLat=3),
+ OpDesc(opClass='SimdFloatDiv', opLat=21),
+ OpDesc(opClass='SimdFloatMisc', opLat=3),
+ OpDesc(opClass='SimdFloatMult', opLat=6),
+ OpDesc(opClass='SimdFloatMultAcc',opLat=1),
+ OpDesc(opClass='SimdFloatSqrt', opLat=9),
+ OpDesc(opClass='FloatAdd', opLat=6),
+ OpDesc(opClass='FloatCmp', opLat=5),
+ OpDesc(opClass='FloatCvt', opLat=5),
+ OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
+ OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
+ OpDesc(opClass='FloatMult', opLat=8) ]
+ count = 2
+
+
+# Load/Store Units
+class ex5_big_Load(FUDesc):
+ opList = [ OpDesc(opClass='MemRead',opLat=2) ]
+ count = 1
+
+class ex5_big_Store(FUDesc):
+ opList = [OpDesc(opClass='MemWrite',opLat=2) ]
+ count = 1
+
+# Functional Units for this CPU
+class ex5_big_FUP(FUPool):
+ FUList = [ex5_big_Simple_Int(), ex5_big_Complex_Int(),
+ ex5_big_Load(), ex5_big_Store(), ex5_big_FP()]
+
+# Bi-Mode Branch Predictor
+class ex5_big_BP(BiModeBP):
+ globalPredictorSize = 4096
+ globalCtrBits = 2
+ choicePredictorSize = 1024
+ choiceCtrBits = 3
+ BTBEntries = 4096
+ BTBTagSize = 18
+ RASSize = 48
+ instShiftAmt = 2
+
+class ex5_big(DerivO3CPU):
+ LQEntries = 16
+ SQEntries = 16
+ LSQDepCheckShift = 0
+ LFSTSize = 1024
+ SSITSize = 1024
+ decodeToFetchDelay = 1
+ renameToFetchDelay = 1
+ iewToFetchDelay = 1
+ commitToFetchDelay = 1
+ renameToDecodeDelay = 1
+ iewToDecodeDelay = 1
+ commitToDecodeDelay = 1
+ iewToRenameDelay = 1
+ commitToRenameDelay = 1
+ commitToIEWDelay = 1
+ fetchWidth = 3
+ fetchBufferSize = 16
+ fetchToDecodeDelay = 3
+ decodeWidth = 3
+ decodeToRenameDelay = 2
+ renameWidth = 3
+ renameToIEWDelay = 1
+ issueToExecuteDelay = 1
+ dispatchWidth = 6
+ issueWidth = 8
+ wbWidth = 8
+ fuPool = ex5_big_FUP()
+ iewToCommitDelay = 1
+ renameToROBDelay = 1
+ commitWidth = 8
+ squashWidth = 8
+ trapLatency = 13
+ backComSize = 5
+ forwardComSize = 5
+ numPhysIntRegs = 90
+ numPhysFloatRegs = 256
+ numIQEntries = 48
+ numROBEntries = 60
+
+ switched_out = False
+ branchPred = ex5_big_BP()
+
+class L1Cache(Cache):
+ tag_latency = 2
+ data_latency = 2
+ response_latency = 2
+ tgts_per_mshr = 8
+ # Consider the L2 a victim cache also for clean lines
+ writeback_clean = True
+
+# Instruction Cache
+class L1I(L1Cache):
+ mshrs = 2
+ size = '32kB'
+ assoc = 2
+ is_read_only = True
+
+# Data Cache
+class L1D(L1Cache):
+ mshrs = 6
+ size = '32kB'
+ assoc = 2
+ write_buffers = 16
+
+# TLB Cache
+# Use a cache as a L2 TLB
+class WalkCache(Cache):
+ tag_latency = 4
+ data_latency = 4
+ response_latency = 4
+ mshrs = 6
+ tgts_per_mshr = 8
+ size = '1kB'
+ assoc = 8
+ write_buffers = 16
+ is_read_only = True
+ # Writeback clean lines as well
+ writeback_clean = True
+
+# L2 Cache
+class L2(Cache):
+ tag_latency = 15
+ data_latency = 15
+ response_latency = 15
+ mshrs = 16
+ tgts_per_mshr = 8
+ size = '2MB'
+ assoc = 16
+ write_buffers = 8
+ prefetch_on_access = True
+ clusivity = 'mostly_excl'
+ # Simple stride prefetcher
+ prefetcher = StridePrefetcher(degree=8, latency = 1)
+ tags = RandomRepl()
+++ /dev/null
-# Copyright (c) 2012 The Regents of The University of Michigan
-# Copyright (c) 2016 Centre National de la Recherche Scientifique
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ron Dreslinski
-# Anastasiia Butko
-# Louisa Bessad
-
-from m5.objects import *
-
-#-----------------------------------------------------------------------
-# ex5 LITTLE core (based on the ARM Cortex-A7)
-#-----------------------------------------------------------------------
-
-# Simple ALU Instructions have a latency of 3
-class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
- opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
-
-# Complex ALU instructions have a variable latencies
-class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
- opList = [ OpDesc(opClass='IntMult', opLat=7) ]
-
-class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
- opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
-
-# Floating point and SIMD instructions
-class ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
- opList = [ OpDesc(opClass='SimdAdd', opLat=6),
- OpDesc(opClass='SimdAddAcc', opLat=4),
- OpDesc(opClass='SimdAlu', opLat=4),
- OpDesc(opClass='SimdCmp', opLat=1),
- OpDesc(opClass='SimdCvt', opLat=3),
- OpDesc(opClass='SimdMisc', opLat=3),
- OpDesc(opClass='SimdMult',opLat=4),
- OpDesc(opClass='SimdMultAcc',opLat=5),
- OpDesc(opClass='SimdShift',opLat=3),
- OpDesc(opClass='SimdShiftAcc', opLat=3),
- OpDesc(opClass='SimdSqrt', opLat=9),
- OpDesc(opClass='SimdFloatAdd',opLat=8),
- OpDesc(opClass='SimdFloatAlu',opLat=6),
- OpDesc(opClass='SimdFloatCmp', opLat=6),
- OpDesc(opClass='SimdFloatCvt', opLat=6),
- OpDesc(opClass='SimdFloatDiv', opLat=20, pipelined=False),
- OpDesc(opClass='SimdFloatMisc', opLat=6),
- OpDesc(opClass='SimdFloatMult', opLat=15),
- OpDesc(opClass='SimdFloatMultAcc',opLat=6),
- OpDesc(opClass='SimdFloatSqrt', opLat=17),
- OpDesc(opClass='FloatAdd', opLat=8),
- OpDesc(opClass='FloatCmp', opLat=6),
- OpDesc(opClass='FloatCvt', opLat=6),
- OpDesc(opClass='FloatDiv', opLat=15, pipelined=False),
- OpDesc(opClass='FloatSqrt', opLat=33),
- OpDesc(opClass='FloatMult', opLat=6) ]
-
-# Load/Store Units
-class ex5_LITTLE_MemFU(MinorDefaultMemFU):
- opList = [ OpDesc(opClass='MemRead',opLat=1),
- OpDesc(opClass='MemWrite',opLat=1) ]
-
-# Misc Unit
-class ex5_LITTLE_MiscFU(MinorDefaultMiscFU):
- opList = [ OpDesc(opClass='IprAccess',opLat=1),
- OpDesc(opClass='InstPrefetch',opLat=1) ]
-
-# Functional Units for this CPU
-class ex5_LITTLE_FUP(MinorFUPool):
- funcUnits = [ex5_LITTLE_Simple_Int(), ex5_LITTLE_Simple_Int(),
- ex5_LITTLE_Complex_IntMul(), ex5_LITTLE_Complex_IntDiv(),
- ex5_LITTLE_FP(), ex5_LITTLE_MemFU(),
- ex5_LITTLE_MiscFU()]
-
-class ex5_LITTLE(MinorCPU):
- executeFuncUnits = ex5_LITTLE_FUP()
-
-class L1Cache(Cache):
- tag_latency = 2
- data_latency = 2
- response_latency = 2
- tgts_per_mshr = 8
- # Consider the L2 a victim cache also for clean lines
- writeback_clean = True
-
-class L1I(L1Cache):
- mshrs = 2
- size = '32kB'
- assoc = 2
- is_read_only = True
- tgts_per_mshr = 20
-
-class L1D(L1Cache):
- mshrs = 4
- size = '32kB'
- assoc = 4
- write_buffers = 4
-
-# TLB Cache
-# Use a cache as a L2 TLB
-class WalkCache(Cache):
- tag_latency = 2
- data_latency = 2
- response_latency = 2
- mshrs = 6
- tgts_per_mshr = 8
- size = '1kB'
- assoc = 2
- write_buffers = 16
- is_read_only = True
- # Writeback clean lines as well
- writeback_clean = True
-
-# L2 Cache
-class L2(Cache):
- tag_latency = 9
- data_latency = 9
- response_latency = 9
- mshrs = 8
- tgts_per_mshr = 12
- size = '512kB'
- assoc = 8
- write_buffers = 16
- prefetch_on_access = True
- clusivity = 'mostly_excl'
- # Simple stride prefetcher
- prefetcher = StridePrefetcher(degree=1, latency = 1)
- tags = RandomRepl()
-
-
+++ /dev/null
-# Copyright (c) 2012 The Regents of The University of Michigan
-# Copyright (c) 2016 Centre National de la Recherche Scientifique
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ron Dreslinski
-# Anastasiia Butko
-# Louisa Bessad
-
-from m5.objects import *
-
-#-----------------------------------------------------------------------
-# ex5 big core (based on the ARM Cortex-A15)
-#-----------------------------------------------------------------------
-
-# Simple ALU Instructions have a latency of 1
-class ex5_big_Simple_Int(FUDesc):
- opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
- count = 2
-
-# Complex ALU instructions have a variable latencies
-class ex5_big_Complex_Int(FUDesc):
- opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True),
- OpDesc(opClass='IntDiv', opLat=11, pipelined=False),
- OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
- count = 1
-
-# Floating point and SIMD instructions
-class ex5_big_FP(FUDesc):
- opList = [ OpDesc(opClass='SimdAdd', opLat=3),
- OpDesc(opClass='SimdAddAcc', opLat=4),
- OpDesc(opClass='SimdAlu', opLat=4),
- OpDesc(opClass='SimdCmp', opLat=4),
- OpDesc(opClass='SimdCvt', opLat=3),
- OpDesc(opClass='SimdMisc', opLat=3),
- OpDesc(opClass='SimdMult',opLat=6),
- OpDesc(opClass='SimdMultAcc',opLat=5),
- OpDesc(opClass='SimdShift',opLat=3),
- OpDesc(opClass='SimdShiftAcc', opLat=3),
- OpDesc(opClass='SimdSqrt', opLat=9),
- OpDesc(opClass='SimdFloatAdd',opLat=6),
- OpDesc(opClass='SimdFloatAlu',opLat=5),
- OpDesc(opClass='SimdFloatCmp', opLat=3),
- OpDesc(opClass='SimdFloatCvt', opLat=3),
- OpDesc(opClass='SimdFloatDiv', opLat=21),
- OpDesc(opClass='SimdFloatMisc', opLat=3),
- OpDesc(opClass='SimdFloatMult', opLat=6),
- OpDesc(opClass='SimdFloatMultAcc',opLat=1),
- OpDesc(opClass='SimdFloatSqrt', opLat=9),
- OpDesc(opClass='FloatAdd', opLat=6),
- OpDesc(opClass='FloatCmp', opLat=5),
- OpDesc(opClass='FloatCvt', opLat=5),
- OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
- OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
- OpDesc(opClass='FloatMult', opLat=8) ]
- count = 2
-
-
-# Load/Store Units
-class ex5_big_Load(FUDesc):
- opList = [ OpDesc(opClass='MemRead',opLat=2) ]
- count = 1
-
-class ex5_big_Store(FUDesc):
- opList = [OpDesc(opClass='MemWrite',opLat=2) ]
- count = 1
-
-# Functional Units for this CPU
-class ex5_big_FUP(FUPool):
- FUList = [ex5_big_Simple_Int(), ex5_big_Complex_Int(),
- ex5_big_Load(), ex5_big_Store(), ex5_big_FP()]
-
-# Bi-Mode Branch Predictor
-class ex5_big_BP(BiModeBP):
- globalPredictorSize = 4096
- globalCtrBits = 2
- choicePredictorSize = 1024
- choiceCtrBits = 3
- BTBEntries = 4096
- BTBTagSize = 18
- RASSize = 48
- instShiftAmt = 2
-
-class ex5_big(DerivO3CPU):
- LQEntries = 16
- SQEntries = 16
- LSQDepCheckShift = 0
- LFSTSize = 1024
- SSITSize = 1024
- decodeToFetchDelay = 1
- renameToFetchDelay = 1
- iewToFetchDelay = 1
- commitToFetchDelay = 1
- renameToDecodeDelay = 1
- iewToDecodeDelay = 1
- commitToDecodeDelay = 1
- iewToRenameDelay = 1
- commitToRenameDelay = 1
- commitToIEWDelay = 1
- fetchWidth = 3
- fetchBufferSize = 16
- fetchToDecodeDelay = 3
- decodeWidth = 3
- decodeToRenameDelay = 2
- renameWidth = 3
- renameToIEWDelay = 1
- issueToExecuteDelay = 1
- dispatchWidth = 6
- issueWidth = 8
- wbWidth = 8
- fuPool = ex5_big_FUP()
- iewToCommitDelay = 1
- renameToROBDelay = 1
- commitWidth = 8
- squashWidth = 8
- trapLatency = 13
- backComSize = 5
- forwardComSize = 5
- numPhysIntRegs = 90
- numPhysFloatRegs = 256
- numIQEntries = 48
- numROBEntries = 60
-
- switched_out = False
- branchPred = ex5_big_BP()
-
-class L1Cache(Cache):
- tag_latency = 2
- data_latency = 2
- response_latency = 2
- tgts_per_mshr = 8
- # Consider the L2 a victim cache also for clean lines
- writeback_clean = True
-
-# Instruction Cache
-class L1I(L1Cache):
- mshrs = 2
- size = '32kB'
- assoc = 2
- is_read_only = True
-
-# Data Cache
-class L1D(L1Cache):
- mshrs = 6
- size = '32kB'
- assoc = 2
- write_buffers = 16
-
-# TLB Cache
-# Use a cache as a L2 TLB
-class WalkCache(Cache):
- tag_latency = 4
- data_latency = 4
- response_latency = 4
- mshrs = 6
- tgts_per_mshr = 8
- size = '1kB'
- assoc = 8
- write_buffers = 16
- is_read_only = True
- # Writeback clean lines as well
- writeback_clean = True
-
-# L2 Cache
-class L2(Cache):
- tag_latency = 15
- data_latency = 15
- response_latency = 15
- mshrs = 16
- tgts_per_mshr = 8
- size = '2MB'
- assoc = 16
- write_buffers = 8
- prefetch_on_access = True
- clusivity = 'mostly_excl'
- # Simple stride prefetcher
- prefetcher = StridePrefetcher(degree=8, latency = 1)
- tags = RandomRepl()
from common import SysPaths
from common import CpuConfig
-from common import ex5_big
-from common import ex5_LITTLE
+from common.cores.arm import ex5_big, ex5_LITTLE
import devices
from devices import AtomicCluster, KvmCluster
from common import FSConfig
from common.Caches import *
from base_config import *
-from common.O3_ARM_v7a import *
+from common.cores.arm.O3_ARM_v7a import *
from common.Benchmarks import SysConfig
class ArmSESystemUniprocessor(BaseSESystemUniprocessor):
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
projects / gem5.git / commitdiff