versa_ecp5: Remove negative diff IO pins

In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)

These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').

Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.

diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
index dbfc26cf587cf5e4d94983b3c51552a7e024a296..7d11e47023a9f1433e005ed5a983fab5499f9d1f 100644 (file)
--- a/litex/boards/platforms/versa_ecp5.py
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -50,9 +50,7 @@ _io = [
             IOStandard("SSTL135_I"),
             Misc("TERMINATION=75")),
         Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
-        Subsignal("dqs_n", Pins("J1 G5"), IOStandard("SSTL135D_I")),
         Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
-        Subsignal("clk_n", Pins("N5"), IOStandard("SSTL135D_I")),
         Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")),
         Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")),
         Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),