break;
case OP_MEMREF2:
- sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
+ sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
p += strlen (p);
comma = ",";
break;
case OP_REG:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) GPR (OP[i]));
+ (uint16_t) GPR (OP[i]));
break;
case OP_REGP:
- tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
+ tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_PROC_REG:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16) CREG (OP[i]));
+ (uint16_t) CREG (OP[i]));
break;
case OP_CONSTANT16:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)OP[i]);
+ (uint16_t)OP[i]);
break;
case OP_CONSTANT4:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)SEXT4(OP[i]));
+ (uint16_t)SEXT4(OP[i]));
break;
case OP_CONSTANT3:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)SEXT3(OP[i]));
+ (uint16_t)SEXT3(OP[i]));
break;
case OP_MEMREF2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)OP[i]);
+ (uint16_t)OP[i]);
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
- (uint16)GPR (OP[i + 1]));
+ (uint16_t)GPR (OP[i + 1]));
i++;
break;
}
#if 0
static void
-trace_output_40 (SIM_DESC sd, uint64 val)
+trace_output_40 (SIM_DESC sd, uint64_t val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
#endif
static void
-trace_output_32 (SIM_DESC sd, uint32 val)
+trace_output_32 (SIM_DESC sd, uint32_t val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
}
static void
-trace_output_16 (SIM_DESC sd, uint16 val)
+trace_output_16 (SIM_DESC sd, uint16_t val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
void
OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp;
- uint8 a = OP[0] & 0xff;
- uint16 b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint16_t b = (GPR (OP[1])) & 0xff;
trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
tmp = (a + b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp;
- uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp;
+ uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = (a + b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xff;
- uint8 b = (GPR (OP[1])) & 0xff;
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = (GPR (OP[0])) & 0xff;
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addub", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
void
OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
void
OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
void
OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b);
trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
void
OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0];
- uint8 b = (GPR (OP[1]) & 0xff);
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = OP[0];
+ uint8_t b = (GPR (OP[1]) & 0xff);
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
void
OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint8 b = (GPR (OP[1]) & 0xff);
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = (OP[0]) & 0xff;
+ uint8_t b = (GPR (OP[1]) & 0xff);
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
void
OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0]) & 0xff);
- uint8 b = (GPR (OP[1]) & 0xff);
- uint16 tmp = (a + b) & 0xff;
+ uint8_t a = (GPR (OP[0]) & 0xff);
+ uint8_t b = (GPR (OP[1]) & 0xff);
+ uint16_t tmp = (a + b) & 0xff;
trace_input ("addb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
void
OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 tmp, b = GPR (OP[1]);
+ int16_t a = OP[0];
+ uint16_t tmp, b = GPR (OP[1]);
tmp = (a + b);
trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
void
OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 tmp, b = GPR (OP[1]);
+ int16_t a = OP[0];
+ uint16_t tmp, b = GPR (OP[1]);
tmp = (a + b);
trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
void
OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("addw", OP_REG, OP_REG, OP_VOID);
tmp = (a + b);
SET_GPR (OP[1], tmp);
void
OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
tmp = (a + b + PSR_C) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int8 a = OP[0] & 0xff;
- uint8 b = (GPR (OP[1])) & 0xff;
- uint8 tmp = (a + b + PSR_C) & 0xff;
+ int8_t a = OP[0] & 0xff;
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp = (a + b + PSR_C) & 0xff;
trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
void
OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xff;
- uint8 b = (GPR (OP[1])) & 0xff;
- uint8 tmp = (a + b + PSR_C) & 0xff;
+ uint8_t a = (GPR (OP[0])) & 0xff;
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp = (a + b + PSR_C) & 0xff;
trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
void
OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b + PSR_C);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b + PSR_C);
trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
void
OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b + PSR_C);
+ int16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b + PSR_C);
trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
void
OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[1]);
- uint16 b = GPR (OP[1]);
- uint16 tmp = (a + b + PSR_C);
+ uint16_t a = GPR (OP[1]);
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (a + b + PSR_C);
trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
void
OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = (OP[0]);
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (a + b);
+ int16_t a = (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (a + b);
trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
void
OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 a = (SEXT16(OP[0]));
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (a + b);
+ int32_t a = (SEXT16(OP[0]));
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (a + b);
trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
void
OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (a + b);
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (a + b);
trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
void
OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = OP[0];
- uint32 b = GPR32 (OP[1]);
- uint32 tmp;
+ uint32_t a = OP[0];
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp;
trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
tmp = (a + b);
SET_GPR32 (OP[1], tmp);
void
OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 a = OP[0];
- uint32 b = GPR32 (OP[1]);
- uint32 tmp;
+ int32_t a = OP[0];
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp;
trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
tmp = (a + b);
SET_GPR32 (OP[1], tmp);
void
OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_REG, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = OP[0], b = GPR (OP[1]);
+ uint16_t tmp, a = OP[0], b = GPR (OP[1]);
trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
void
OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = OP[0], b = GPR (OP[1]);
+ uint16_t tmp, a = OP[0], b = GPR (OP[1]);
trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
void
OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
+ uint16_t tmp, a = GPR (OP[0]), b = GPR (OP[1]);
trace_input ("andw", OP_REG, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
void
OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
+ uint32_t tmp, a = OP[0], b = GPR32 (OP[1]);
trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
tmp = a & b;
SET_GPR32 (OP[1], tmp);
void
OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
+ uint32_t tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
tmp = a & b;
SET_GPR32 (OP[1], tmp);
void
OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR32 (OP[1], tmp);
void
OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
tmp = a | b;
SET_GPR32 (OP[1], tmp);
void
OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR32 (OP[1], tmp);
void
OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+ uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
tmp = a ^ b;
SET_GPR32 (OP[1], tmp);
void
OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0, cc = cond_stat (OP[0]);
+ uint32_t tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
if (cc)
{
void
OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0, cc = cond_stat (OP[0]);
+ uint32_t tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
if (cc)
{
void
OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0, cc = cond_stat (OP[0]);
+ uint32_t tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
if (cc)
{
void
OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
SET_GPR32 (14, tmp);
void
OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
SET_GPR32 (OP[0], tmp);
void
OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
tmp = GPR32 (OP[1]);
void
OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
tmp = GPR32 (OP[0]);
void
OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint8 a = (GPR (OP[0]) & 0xFF);
+ uint32_t addr;
+ uint8_t a = (GPR (OP[0]) & 0xFF);
trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a == 0)
void
OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint8 a = (GPR (OP[0]) & 0xFF);
+ uint32_t addr;
+ uint8_t a = (GPR (OP[0]) & 0xFF);
trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a != 0)
void
OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = GPR (OP[0]);
+ uint32_t addr;
+ uint16_t a = GPR (OP[0]);
trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a == 0)
void
OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = GPR (OP[0]);
+ uint32_t addr;
+ uint16_t a = GPR (OP[0]);
trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a != 0)
void
OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_Z) == 1)
{
void
OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_Z) == 0)
{
void
OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_C) == 1)
{
void
OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_C) == 0)
{
void
OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_L) == 1)
{
void
OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_L) == 0)
{
void
OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_N) == 1)
{
void
OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_N) == 0)
{
void
OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_F) == 1)
{
void
OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_F) == 0)
{
void
OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_L) == 0))
{
void
OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 1) | ((PSR_L) == 1))
{
void
OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_N) == 0))
{
void
OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = 0;
+ uint32_t tmp = 0;
trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 1) | ((PSR_N) == 1))
{
void
OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
void
OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
void
OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = (OP[0]), tmp;
+ uint32_t addr;
+ uint16_t a = (OP[0]), tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
void
OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = (OP[0]), tmp;
+ uint32_t addr;
+ uint16_t a = (OP[0]), tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
void
OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xff;
- uint32 addr = OP[1], tmp;
+ uint8_t a = OP[0] & 0xff;
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1], tmp;
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = (OP[0]), tmp;
+ uint32_t addr;
+ uint16_t a = (OP[0]), tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
void
OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
+ uint16_t a = (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
void
OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = (GPR (OP[1]));
+ uint16_t a = OP[0];
+ uint16_t b = (GPR (OP[1]));
trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_F (b & (1 << a));
trace_output_16 (sd, b);
void
OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = (GPR (OP[1]));
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = (GPR (OP[1]));
trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
SET_PSR_F (b & (1 << a));
trace_output_16 (sd, b);
void
OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
+ uint8_t a = (OP[0]) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int8)a > (int8)b);
+ SET_PSR_N ((int8_t)a > (int8_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
+ uint8_t a = (OP[0]) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int8)a > (int8)b);
+ SET_PSR_N ((int8_t)a > (int8_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
+ uint8_t a = (GPR (OP[0])) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int8)a > (int8)b);
+ SET_PSR_N ((int8_t)a > (int8_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint16 b = GPR (OP[1]);
+ uint16_t a = (OP[0]);
+ uint16_t b = GPR (OP[1]);
trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int16)a > (int16)b);
+ SET_PSR_N ((int16_t)a > (int16_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (OP[0]);
- uint16 b = GPR (OP[1]);
+ uint16_t a = (OP[0]);
+ uint16_t b = GPR (OP[1]);
trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int16)a > (int16)b);
+ SET_PSR_N ((int16_t)a > (int16_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]) ;
- uint16 b = GPR (OP[1]) ;
+ uint16_t a = GPR (OP[0]) ;
+ uint16_t b = GPR (OP[1]) ;
trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int16)a > (int16)b);
+ SET_PSR_N ((int16_t)a > (int16_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = (OP[0]);
- uint32 b = GPR32 (OP[1]);
+ uint32_t a = (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = (SEXT16(OP[0]));
- uint32 b = GPR32 (OP[1]);
+ uint32_t a = (SEXT16(OP[0]));
+ uint32_t b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]) ;
- uint32 b = GPR32 (OP[1]) ;
+ uint32_t a = GPR32 (OP[0]) ;
+ uint32_t b = GPR32 (OP[1]) ;
trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = (OP[0]);
- uint32 b = GPR32 (OP[1]);
+ uint32_t a = (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
- SET_PSR_N ((int32)a > (int32)b);
+ SET_PSR_N ((int32_t)a > (int32_t)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
void
OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = OP[0] & 0xFF;
- uint16 a = (GPR (OP[1])) & 0xFF00;
+ uint8_t tmp = OP[0] & 0xFF;
+ uint16_t a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
void
OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = OP[0] & 0xFF;
- uint16 a = (GPR (OP[1])) & 0xFF00;
+ uint8_t tmp = OP[0] & 0xFF;
+ uint16_t a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
void
OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = (GPR (OP[0])) & 0xFF;
- uint16 a = (GPR (OP[1])) & 0xFF00;
+ uint8_t tmp = (GPR (OP[0])) & 0xFF;
+ uint16_t a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
void
OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = OP[0];
+ uint16_t tmp = OP[0];
trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp & 0xffff));
trace_output_16 (sd, tmp);
void
OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp = OP[0];
+ int16_t tmp = OP[0];
trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp & 0xffff));
trace_output_16 (sd, tmp);
void
OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]);
- uint32 a = GPR32 (OP[1]);
+ uint16_t tmp = GPR (OP[0]);
+ uint32_t a = GPR32 (OP[1]);
trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
a = (a & 0xffff0000) | tmp;
SET_GPR32 (OP[1], a);
void
OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = (GPR (OP[0])) & 0xFF;
+ uint8_t tmp = (GPR (OP[0])) & 0xFF;
trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
trace_output_16 (sd, tmp);
void
OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp = (GPR (OP[0])) & 0xFF;
+ uint8_t tmp = (GPR (OP[0])) & 0xFF;
trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
void
OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]);
+ uint16_t tmp = GPR (OP[0]);
trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], SEXT16(tmp));
trace_output_16 (sd, tmp);
void
OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp = GPR (OP[0]);
+ uint16_t tmp = GPR (OP[0]);
trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
trace_output_16 (sd, tmp);
void
OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp = OP[0];
+ int32_t tmp = OP[0];
trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
void
OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp = SEXT16(OP[0]);
+ int32_t tmp = SEXT16(OP[0]);
trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
void
OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = GPR32 (OP[0]);
+ uint32_t tmp = GPR32 (OP[0]);
trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
void
OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp = OP[0];
+ uint32_t tmp = OP[0];
trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
void
OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp = OP[0];
+ int32_t tmp = OP[0];
trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
void
OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR (0);
- uint16 count = OP[0], reg = 2, tmp;
+ uint32_t addr = GPR (0);
+ uint16_t count = OP[0], reg = 2, tmp;
trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
void
OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR32 (0);
- uint16 count = OP[0], reg = 2, tmp;
+ uint32_t addr = GPR32 (0);
+ uint16_t count = OP[0], reg = 2, tmp;
trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
- uint32 addr = OP[0];
+ uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
+ uint32_t addr = OP[0];
trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
if (addr > 0xEFFFF) addr |= 0xF00000;
tmp = (RB (addr));
* ADDR = abs24
* REGR = [ADDR]. */
- uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
- uint32 addr = OP[0];
+ uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
+ uint32_t addr = OP[0];
trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[1], (a | tmp));
* ADDR = Rindex + zext24(disp20)
* REGR = [ADDR]. */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
if (OP[0] == 0)
/* loadb DIPS4(REGP) REG
* ADDR = RPBASE + zext24(DISP4)
* REG = [ADDR]. */
- uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[0];
+ uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
* ADDR = Rpbasex + Rindex
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
* ADDR = Rpbasex + Rindex + zext24(disp14)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
addr = (GPR32 (OP[2])) + OP[1];
* zext24(Rbase) + zext24(dispe20)
* REG = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = OP[0] + (GPR (OP[1]));
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = OP[0] + (GPR (OP[1]));
trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
* ADDR = zext24(Rbase) + zext24(disp20)
* REG = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = OP[0] + (GPR (OP[1]));
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = OP[0] + (GPR (OP[1]));
trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
* ADDR = RPbase + zext24(disp16)
* REGR = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[0];
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
/* loadb disp20(REGP) REG
* ADDR = RPbase + zext24(disp20)
* REGR = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[0];
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
/* loadb -disp20(REGP) REG
* ADDR = RPbase + zext24(-disp20)
* REGR = [ADDR] */
- uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
- uint32 addr = (GPR32 (OP[1])) + OP[1];
+ uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
+ uint32_t addr = (GPR32 (OP[1])) + OP[1];
trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
tmp = (RB (addr));
SET_GPR (OP[2], (a | tmp));
* ADDR = RPbasex + Rindex + zext24(disp20)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
+ uint32_t addr;
+ uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint16 tmp;
- uint32 addr = OP[0];
+ uint16_t tmp;
+ uint32_t addr = OP[0];
trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
if (addr > 0xEFFFF) addr |= 0xF00000;
tmp = (RW (addr));
/* loadw ABS24, REG
* ADDR = abs24
* REGR = [ADDR] */
- uint16 tmp;
- uint32 addr = OP[0];
+ uint16_t tmp;
+ uint32_t addr = OP[0];
trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
tmp = (RW (addr));
SET_GPR (OP[1], tmp);
* ADDR = Rindex + zext24(disp20)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
if (OP[0] == 0)
/* loadw DIPS4(REGP) REGP
* ADDR = RPBASE + zext24(DISP4)
* REGP = [ADDR]. */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RW (addr));
* ADDR = Rpbasex + Rindex
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
* ADDR = Rpbasex + Rindex + zext24(disp14)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
addr = (GPR32 (OP[2])) + OP[1];
/* loadw dispe20(REG) REGP
* REGP = [DISPE20+[REG]] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
addr = OP[0] + (GPR (OP[1]));
tmp = (RW (addr));
* ADDR = zext24(Rbase) + zext24(disp20)
* REGP = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
addr = OP[0] + (GPR (OP[1]));
tmp = (RW (addr));
/* loadw disp16(REGP) REGP
* ADDR = RPbase + zext24(disp16)
* REGP = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RW (addr));
/* loadw disp20(REGP) REGP
* ADDR = RPbase + zext24(disp20)
* REGP = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RW (addr));
* ADDR = RPbase + zext24(-disp20)
* REGR = [ADDR] */
- uint16 tmp;
- uint32 addr, a;
+ uint16_t tmp;
+ uint32_t addr, a;
trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
addr = (GPR32 (OP[1])) + OP[0];
tmp = (RB (addr));
* ADDR = RPbasex + Rindex + zext24(disp20)
* REGR = [ADDR] */
- uint32 addr;
- uint16 tmp;
+ uint32_t addr;
+ uint16_t tmp;
trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
if (OP[0] == 0)
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
addr = OP[0];
trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
if (addr > 0xEFFFF) addr |= 0xF00000;
* ADDR = abs24
* REGP = [ADDR] */
- uint32 addr = OP[0];
- uint32 tmp;
+ uint32_t addr = OP[0];
+ uint32_t tmp;
trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
* ADDR = Rindex + zext24(disp20)
* REGP = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
if (OP[0] == 0)
* ADDR = Rpbase + zext24(disp4)
* REGP = [ADDR] */
- uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
+ uint32_t tmp, addr = (GPR32 (OP[1])) + OP[0];
trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
* ADDR = Rpbasex + Rindex
* REGP = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
if (OP[0] == 0)
* ADDR = Rpbasex + Rindex + zext24(disp14)
* REGR = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
if (OP[0] == 0)
* zext24(Rbase) + zext24(dispe20)
* REG = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
* ADDR = zext24(Rbase) + zext24(disp20)
* REG = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
/* loadd disp16(REGP) REGP
* ADDR = RPbase + zext24(disp16)
* REGR = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
/* loadd disp20(REGP) REGP
* ADDR = RPbase + zext24(disp20)
* REGP = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
* ADDR = RPbase + zext24(-disp20)
* REGP = [ADDR] */
- uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
+ uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
tmp = RLW (addr);
tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
* ADDR = RPbasex + Rindex + zext24(disp20)
* REGP = [ADDR] */
- uint32 addr, tmp;
+ uint32_t addr, tmp;
trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
if (OP[0] == 0)
* with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
* by the core to 16M-64k to 16M. */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = OP[1];
trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = abs24
* [ADDR] = REGR. */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = OP[1];
trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = Rindex + zext24(disp20)
* [ADDR] = REGR */
- uint32 addr;
- uint8 a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr;
+ uint8_t a = ((GPR (OP[0])) & 0xff);
trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
* ADDR = RPBASE + zext24(DISP4)
* [ADDR] = REG. */
- uint16 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = Rpbasex + Rindex
* [ADDR] = REGR */
- uint32 addr;
- uint8 a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr;
+ uint8_t a = ((GPR (OP[0])) & 0xff);
trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
if (OP[1] == 0)
* ADDR = Rpbasex + Rindex + zext24(disp14)
* [ADDR] = REGR */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* zext24(Rbase) + zext24(dispe20)
* [ADDR] = REG */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = OP[1] + (GPR (OP[2]));
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = OP[1] + (GPR (OP[2]));
trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = zext24(Rbase) + zext24(disp20)
* [ADDR] = REG */
- uint8 a = (GPR (OP[0]) & 0xff);
- uint32 addr = OP[1] + (GPR (OP[2]));
+ uint8_t a = (GPR (OP[0]) & 0xff);
+ uint32_t addr = OP[1] + (GPR (OP[2]));
trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = RPbase + zext24(disp16)
* [ADDR] = REGP */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = RPbase + zext24(disp20)
* [ADDR] = REGP */
- uint8 a = ((GPR (OP[0])) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = ((GPR (OP[0])) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = RPbase + zext24(-disp20)
* [ADDR] = REGP */
- uint8 a = (GPR (OP[0]) & 0xff);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (GPR (OP[0]) & 0xff);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
* ADDR = RPbasex + Rindex + zext24(disp20)
* [ADDR] = REGP */
- uint8 a = (GPR (OP[0])) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (GPR (OP[0])) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = OP[1];
trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = OP[1];
trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint8 a = (OP[0]) & 0xff;
+ uint32_t addr;
+ uint8_t a = (OP[0]) & 0xff;
trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
void
OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (OP[0]) & 0xff;
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint8_t a = (OP[0]) & 0xff;
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
SB (addr, a);
trace_output_32 (sd, addr);
void
OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = GPR (OP[0]);
+ uint32_t addr;
+ uint16_t a = GPR (OP[0]);
trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
void
OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = GPR (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0]));
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = (GPR (OP[0]));
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1];
trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = OP[1];
trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr;
- uint16 a = OP[0];
+ uint32_t addr;
+ uint16_t a = OP[0];
trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
void
OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint16_t a = OP[0];
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
SW (addr, a);
trace_output_32 (sd, addr);
void
OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = OP[1];
trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr, a = GPR32 (OP[0]);
+ uint32_t addr, a = GPR32 (OP[0]);
trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
void
OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 addr = (GPR32 (OP[2])) + OP[1];
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t addr = (GPR32 (OP[2])) + OP[1];
trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
SLW (addr, a);
trace_output_32 (sd, addr);
void
OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 src1, src2;
+ int32_t tmp;
+ int16_t src1, src2;
trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
src1 = GPR (OP[0]);
src2 = GPR (OP[1]);
void
OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
- uint16 src1, src2;
+ uint32_t tmp;
+ uint16_t src1, src2;
trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
src1 = GPR (OP[0]);
src2 = GPR (OP[1]);
void
OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 src1, src2;
+ int32_t tmp;
+ int16_t src1, src2;
trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
src1 = GPR (OP[0]);
src2 = GPR (OP[1]);
void
OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (OP[0]) & 0xff;
- int8 b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (OP[0]) & 0xff;
+ int8_t b = (GPR (OP[1])) & 0xff;
trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
tmp = (a * b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = (a * b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
tmp = (a * b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- uint16 a = OP[0];
- int16 b = (GPR (OP[1]));
+ int32_t tmp;
+ uint16_t a = OP[0];
+ int16_t b = (GPR (OP[1]));
trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
tmp = (a * b) & 0xffff;
SET_GPR (OP[1], tmp);
void
OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 a = OP[0], b = (GPR (OP[1]));
+ int32_t tmp;
+ int16_t a = OP[0], b = (GPR (OP[1]));
trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = (a * b) & 0xffff;
SET_GPR (OP[1], tmp);
void
OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+ int32_t tmp;
+ int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
tmp = (a * b) & 0xffff;
SET_GPR (OP[1], tmp);
void
OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ int16_t tmp;
+ int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
tmp = a * b;
SET_GPR (OP[1], tmp);
void
OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+ int32_t tmp;
+ int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
tmp = a * b;
SET_GPR32 (OP[1], tmp);
void
OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
- uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint32_t tmp;
+ uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
tmp = a * b;
SET_GPR32 (OP[1], tmp);
void
OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
void
OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
void
OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("orb", OP_REG, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
void
OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], tmp);
void
OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], tmp);
void
OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("orw", OP_REG, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR (OP[1], tmp);
void
OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = OP[0];
+ uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0])) & 0xff;
- uint16 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = (GPR (OP[0])) & 0xff;
+ uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 3))
{
void
OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, b = GPR (OP[1]);
- int16 a = GPR (OP[0]);
+ uint16_t tmp, b = GPR (OP[1]);
+ int16_t a = GPR (OP[0]);
trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 4))
{
void
OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, b = GPR (OP[1]);
- uint16 a = OP[0];
+ uint16_t tmp, b = GPR (OP[1]);
+ uint16_t a = OP[0];
trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, b = GPR32 (OP[1]);
- uint16 a = OP[0];
+ uint32_t tmp, b = GPR32 (OP[1]);
+ uint16_t a = OP[0];
trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp, b = GPR32 (OP[1]);
- uint16 a = GPR (OP[0]);
+ uint32_t tmp, b = GPR32 (OP[1]);
+ uint16_t a = GPR (OP[0]);
trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
if (a & ((long)1 << 5))
{
void
OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- int8 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = OP[0];
+ int8_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- int8 tmp, b = (GPR (OP[1])) & 0xFF;
+ uint16_t a = OP[0];
+ int8_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = (GPR (OP[0]));
- int8 tmp, b = (GPR (OP[1])) & 0xFF;
+ int16_t a = (GPR (OP[0]));
+ int8_t tmp, b = (GPR (OP[1])) & 0xFF;
trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 3))
void
OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp, b = GPR (OP[1]);
- uint16 a = OP[0];
+ int16_t tmp, b = GPR (OP[1]);
+ uint16_t a = OP[0];
trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp, b = GPR (OP[1]);
- uint16 a = OP[0];
+ int16_t tmp, b = GPR (OP[1]);
+ uint16_t a = OP[0];
trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 tmp;
- int16 a = GPR (OP[0]), b = GPR (OP[1]);
+ int16_t tmp;
+ int16_t a = GPR (OP[0]), b = GPR (OP[1]);
trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
if (a & ((long)1 << 4))
void
OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp,b = GPR32 (OP[1]);
- uint32 a = OP[0];
+ int32_t tmp,b = GPR32 (OP[1]);
+ uint32_t a = OP[0];
trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int32 a = OP[0], b = GPR32 (OP[1]);
+ int32_t tmp;
+ int32_t a = OP[0], b = GPR32 (OP[1]);
trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
/* A positive count specifies a shift to the left;
* A negative count specifies a shift to the right. */
void
OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 tmp;
- int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
+ int32_t tmp;
+ int32_t a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
if (a & ((long)1 << 5))
void
OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR (1);
- uint16 count = OP[0], reg = 2;
+ uint32_t addr = GPR (1);
+ uint16_t count = OP[0], reg = 2;
trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
void
OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 addr = GPR32 (6);
- uint16 count = OP[0], reg = 2;
+ uint32_t addr = GPR32 (6);
+ uint16_t count = OP[0], reg = 2;
trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
if ((addr & 1))
{
void
OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0];
- uint8 b = (GPR (OP[1])) & 0xff;
- uint16 tmp = (~a + 1 + b) & 0xff;
+ uint8_t a = OP[0];
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp = (~a + 1 + b) & 0xff;
trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0] & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
- uint16 tmp = (~a + 1 + b) & 0xFF;
+ uint8_t a = OP[0] & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
+ uint16_t tmp = (~a + 1 + b) & 0xFF;
trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = (GPR (OP[0])) & 0xFF;
- uint8 b = (GPR (OP[1])) & 0xFF;
- uint16 tmp = (~a + 1 + b) & 0xff;
+ uint8_t a = (GPR (OP[0])) & 0xFF;
+ uint8_t b = (GPR (OP[1])) & 0xFF;
+ uint16_t tmp = (~a + 1 + b) & 0xff;
trace_input ("subb", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp = (~a + 1 + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp = (~a + 1 + b);
trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ uint16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
- uint16 b = GPR (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ uint16_t a = GPR (OP[0]);
+ uint16_t b = GPR (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subw", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 a = OP[0];
- uint8 b = (GPR (OP[1])) & 0xff;
- //uint16 tmp1 = a + 1;
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint8_t a = OP[0];
+ uint8_t b = (GPR (OP[1])) & 0xff;
+ //uint16_t tmp1 = a + 1;
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0];
- uint16 b = (GPR (OP[1])) & 0xff;
- //uint16 tmp1 = a + 1;
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = OP[0];
+ uint16_t b = (GPR (OP[1])) & 0xff;
+ //uint16_t tmp1 = a + 1;
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0])) & 0xff;
- uint16 b = (GPR (OP[1])) & 0xff;
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = (GPR (OP[0])) & 0xff;
+ uint16_t b = (GPR (OP[1])) & 0xff;
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0], b = (GPR (OP[1]));
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = OP[0], b = (GPR (OP[1]));
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int16 a = OP[0];
- uint16 b = GPR (OP[1]);
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ int16_t a = OP[0];
+ uint16_t b = GPR (OP[1]);
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
- uint16 tmp1 = a + (PSR_C);
- uint16 tmp = (~tmp1 + 1 + b);
+ uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp1 = a + (PSR_C);
+ uint16_t tmp = (~tmp1 + 1 + b);
trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
{
- int32 a = OP[0];
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ int32_t a = OP[0];
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
void
OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
- uint32 b = GPR32 (OP[1]);
- uint32 tmp = (~a + 1 + b);
+ uint32_t a = GPR32 (OP[0]);
+ uint32_t b = GPR32 (OP[1]);
+ uint32_t tmp = (~a + 1 + b);
trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits. */
OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
{
host_callback *cb = STATE_CALLBACK (sd);
- uint32 tmp;
- uint16 a;
+ uint32_t tmp;
+ uint16_t a;
trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
switch (OP[0])
{
#if (DEBUG & DEBUG_TRAP) == 0
{
#if 0
- uint16 vec = OP[0] + TRAP_VECTOR_START;
+ uint16_t vec = OP[0] + TRAP_VECTOR_START;
SET_BPC (PC + 1);
SET_BPSR (PSR);
SET_PSR (PSR & PSR_SM_BIT);
case 8: /* new system call trap */
/* Trap 8 is used for simulating low-level I/O */
{
- unsigned32 result = 0;
+ uint32_t result = 0;
errno = 0;
/* Registers passed to trap 0. */
buf = PARM1;
RETVAL (pipe (host_fd));
SW (buf, host_fd[0]);
- buf += sizeof(uint16);
+ buf += sizeof(uint16_t);
SW (buf, host_fd[1]);
trace_output_16 (sd, result);
}
break;
}
}
- if ((uint16) result == (uint16) -1)
+ if ((uint16_t) result == (uint16_t) -1)
RETERR (cb->get_errno (cb));
else
RETERR (0);
void
OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
- uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
for (; i < a; ++i)
void
OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 sp_addr, tmp, is_regp = 0;
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t sp_addr, tmp, is_regp = 0;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
if (c == 1)
void
OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 sp_addr = (GPR32 (15)), tmp;
+ uint32_t sp_addr = (GPR32 (15)), tmp;
trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
tmp = (GPR32 (14));
SLW(sp_addr-4,tmp); /* Store RA address. */
void
OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
- uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
for (; i < a; ++i)
void
OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
- uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
+ uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
+ uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;
trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
for (; i < a; ++i)
void
OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 sp_addr = GPR32 (15);
- uint32 tmp;
+ uint32_t sp_addr = GPR32 (15);
+ uint32_t tmp;
trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
tmp = RLW(sp_addr);
void
OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0], b = OP[1];
+ uint16_t a = OP[0], b = OP[1];
trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
OP_5_9 (sd, cpu);
JMP(((GPR32(14)) << 1) & 0xffffff);
void
OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = OP[0], b = OP[1];
+ uint16_t a = OP[0], b = OP[1];
trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
OP_2_8 (sd, cpu);
JMP(((GPR32(14)) << 1) & 0xffffff);
void
OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 tmp;
+ uint32_t tmp;
trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
OP_21E_10 (sd, cpu);
tmp = (((GPR32(14)) << 1) & 0xffffff);
void
OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
+ uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
void
OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], tmp);
void
OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
+ uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], tmp);
void
OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
+ uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR (OP[1], tmp);
void
OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = GPR (OP[0]);
+ uint16_t a = GPR (OP[0]);
trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
SET_CREG (OP[1], a);
trace_output_16 (sd, a);
void
OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = GPR32 (OP[0]);
+ uint32_t a = GPR32 (OP[0]);
trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
SET_CREG (OP[1], a);
trace_output_flag (sd);
void
OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint16 a = CREG (OP[0]);
+ uint16_t a = CREG (OP[0]);
trace_input ("spr", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], a);
trace_output_16 (sd, a);
void
OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
{
- uint32 a = CREG (OP[0]);
+ uint32_t a = CREG (OP[0]);
trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], a);
trace_output_32 (sd, a);
projects / binutils-gdb.git / commitdiff