intel/gen_decoder: Decode SLICE_HASH_TABLE.

diff --git a/src/intel/common/gen_batch_decoder.c b/src/intel/common/gen_batch_decoder.c
index e44c352a05361f5e444e7bd9b9e9bb8817688a6c..5dc38c86ef3c24f1e7ff4ee4cc44eb31698feeb5 100644 (file)
--- a/src/intel/common/gen_batch_decoder.c
+++ b/src/intel/common/gen_batch_decoder.c
@@ -752,6 +752,13 @@ decode_3dstate_scissor_state_pointers(struct gen_batch_decode_ctx *ctx,
    decode_dynamic_state_pointers(ctx, "SCISSOR_RECT", p, 1);
 }
 
+static void
+decode_3dstate_slice_table_state_pointers(struct gen_batch_decode_ctx *ctx,
+                                          const uint32_t *p)
+{
+   decode_dynamic_state_pointers(ctx, "SLICE_HASH_TABLE", p, 1);
+}
+
 static void
 decode_load_register_imm(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
 {
@@ -801,6 +808,7 @@ struct custom_decoder {
    { "3DSTATE_BLEND_STATE_POINTERS", decode_3dstate_blend_state_pointers },
    { "3DSTATE_CC_STATE_POINTERS", decode_3dstate_cc_state_pointers },
    { "3DSTATE_SCISSOR_STATE_POINTERS", decode_3dstate_scissor_state_pointers },
+   { "3DSTATE_SLICE_TABLE_STATE_POINTERS", decode_3dstate_slice_table_state_pointers },
    { "MI_LOAD_REGISTER_IMM", decode_load_register_imm }
 };