use the new isPublic() in a few places

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 81a3f483bba1709026ca18b45791fac35a506473..476b30488d269aee32ff68a9c4e1c8d9bd61f7e7 100644 (file)
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -111,7 +111,7 @@ struct AigerWriter
 
                // promote public wires
                for (auto wire : module->wires())
-                       if (wire->name[0] == '\\')
+                       if (wire->name.isPublic())
                                sigmap.add(wire);
 
                // promote input wires

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ef0103c179b9c0c7b984bc06b9debf12cd237887..27499b64a7aa8ec0c03e658e7bf6b5e762f5e9a9 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -146,7 +146,7 @@ struct XAigerWriter
 
                // promote public wires
                for (auto wire : module->wires())
-                       if (wire->name[0] == '\\')
+                       if (wire->name.isPublic())
                                sigmap.add(wire);
 
                // promote input wires

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 5e6becfd03d3abfac8985a097b04fd1fc11ae51c..e0013238c8321b320de162fc86df6a397f6b03f3 100644 (file)
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -330,7 +330,7 @@ struct EdifBackend : public Backend {
                                }
                                *f << stringf("\n            (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
                        }
-               };              
+               };
                for (auto module : sorted_modules)
                {
                        if (module->get_blackbox_attribute())
@@ -373,8 +373,8 @@ struct EdifBackend : public Backend {
                                        }
 
                                        {
-                                               int c1 = w1->name[0] == '\\';
-                                               int c2 = w2->name[0] == '\\';
+                                               int c1 = w1->name.isPublic();
+                                               int c2 = w2->name.isPublic();
 
                                                if (c1 > c2) goto promote;
                                                if (c1 < c2) goto nopromote;
@@ -524,7 +524,7 @@ struct EdifBackend : public Backend {
                                                *f << stringf("            (portRef %c (instanceRef GND))\n", gndvccy ? 'Y' : 'G');
                                        if (sig == RTLIL::State::S1)
                                                *f << stringf("            (portRef %c (instanceRef VCC))\n", gndvccy ? 'Y' : 'P');
-                               }                               
+                               }
                                *f << stringf("            )");
                                if (attr_properties && sig.wire != NULL)
                                        for (auto &p : sig.wire->attributes)

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 4a53ce6d5d416c3b1a7d90f89086a77c33baff71..0b4e20ac63f5531938572b82c58c63158ad607dd 100644 (file)
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -822,7 +822,7 @@ struct Smt2Worker
                        for (auto bit : SigSpec(wire))
                                if (reg_bits.count(bit))
                                        is_register = true;
-                       if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) {
+                       if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name.isPublic())) {
                                RTLIL::SigSpec sig = sigmap(wire);
                                std::vector<std::string> comments;
                                if (wire->port_input)
@@ -831,7 +831,7 @@ struct Smt2Worker
                                        comments.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width));
                                if (is_register)
                                        comments.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width));
-                               if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\'))
+                               if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name.isPublic()))
                                        comments.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width));
                                if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig)))
                                        comments.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 6326b4b15d2a750bc018615b931b97f4a71b5354..f8fe715c8e2a006edeb638723c87f29e8cd3524e 100644 (file)
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -290,11 +290,11 @@ struct RenamePass : public Pass {
                                dict<RTLIL::Cell *, IdString> new_cell_names;
 
                                for (auto wire : module->selected_wires())
-                                       if (wire->name[0] == '\\' && wire->port_id == 0)
+                                       if (wire->name.isPublic() && wire->port_id == 0)
                                                new_wire_names[wire] = NEW_ID;
 
                                for (auto cell : module->selected_cells())
-                                       if (cell->name[0] == '\\')
+                                       if (cell->name.isPublic())
                                                new_cell_names[cell] = NEW_ID;
 
                                for (auto &it : new_wire_names)

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index a4ad861f62437dea41891af991c0ec4358966e28..0c96f8c5d4dedeefba8904340c0fd91608862f23 100644 (file)
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -368,7 +368,7 @@ struct ShowWorker
                        const char *shape = "diamond";
                        if (wire->port_input || wire->port_output)
                                shape = "octagon";
-                       if (wire->name[0] == '\\') {
+                       if (wire->name.isPublic()) {
                                fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
                                                id2num(wire->name), shape, findLabel(wire->name.str()),
                                                nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str());

diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 20627d601e7818be892e26095b27e21093ba5a15..0f63b91c574f08b37057fb0a775836ba7441c595 100644 (file)
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -211,7 +211,7 @@ struct SpliceWorker
                std::vector<Wire*> mod_wires = module->wires();
 
                for (auto wire : mod_wires)
-                       if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) {
+                       if ((!no_outputs && wire->port_output) || (do_wires && wire->name.isPublic())) {
                                if (!design->selected(module, wire))
                                        continue;
                                RTLIL::SigSpec sig = sigmap(wire);

diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index ed51fdc24727d2eb20cd628ae259148bc45b7887..0d84c73db3755cd7b58a4ecd63e8361aeeee8af5 100644 (file)
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -81,7 +81,7 @@ struct statdata_t
 
                for (auto wire : mod->selected_wires())
                {
-                       if (wire->name[0] == '\\') {
+                       if (wire->name.isPublic()) {
                                num_pub_wires++;
                                num_pub_wire_bits += wire->width;
                        }

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 51b4ad0f1362f9f4212e7d5e3abccf45bb0544d8..6923ae3d01fc9c36c1193f794660f4830f793c68 100644 (file)
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -114,25 +114,25 @@ struct EquivMakeWorker
                Module *gate_clone = gate_mod->clone();
 
                for (auto it : gold_clone->wires().to_vector()) {
-                       if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+                       if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
                                wire_names.insert(it->name);
                        gold_clone->rename(it, it->name.str() + "_gold");
                }
 
                for (auto it : gold_clone->cells().to_vector()) {
-                       if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+                       if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
                                cell_names.insert(it->name);
                        gold_clone->rename(it, it->name.str() + "_gold");
                }
 
                for (auto it : gate_clone->wires().to_vector()) {
-                       if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+                       if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
                                wire_names.insert(it->name);
                        gate_clone->rename(it, it->name.str() + "_gate");
                }
 
                for (auto it : gate_clone->cells().to_vector()) {
-                       if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0)
+                       if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
                                cell_names.insert(it->name);
                        gate_clone->rename(it, it->name.str() + "_gate");
                }

diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index d15c8d1836bfce0703e0b9653965a46da32e62c9..a43ecec5a936fb38dcc5914c504649d1df472da2 100644 (file)
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -35,7 +35,7 @@ struct EquivPurgeWorker
        {
                if (sig.is_wire()) {
                        Wire *wire = sig.as_wire();
-                       if (wire->name[0] == '\\') {
+                       if (wire->name.isPublic()) {
                                if (!wire->port_output) {
                                        log("  Module output: %s (%s)\n", log_signal(wire), log_id(cellname));
                                        wire->port_output = true;
@@ -62,7 +62,7 @@ struct EquivPurgeWorker
        {
                if (sig.is_wire()) {
                        Wire *wire = sig.as_wire();
-                       if (wire->name[0] == '\\') {
+                       if (wire->name.isPublic()) {
                                if (!wire->port_output) {
                                        log("  Module input: %s\n", log_signal(wire));
                                        wire->port_input = true;

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 5370881d3f1c723a8efcdaebad36f89f0542fc49..bd9856e81c89f7bd03e861c518c1390af243f446 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -207,7 +207,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
        if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
                return !(w2->port_input && w2->port_output);
 
-       if (w1->name[0] == '\\' && w2->name[0] == '\\') {
+       if (w1->name.isPublic() && w2->name.isPublic()) {
                if (regs.check(s1) != regs.check(s2))
                        return regs.check(s2);
                if (direct_wires.count(w1) != direct_wires.count(w2))
@@ -220,7 +220,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
                return w2->port_output;
 
        if (w1->name[0] != w2->name[0])
-               return w2->name[0] == '\\';
+               return w2->name.isPublic();
 
        int attrs1 = count_nontrivial_wire_attrs(w1);
        int attrs2 = count_nontrivial_wire_attrs(w2);

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 15abee73ed4e07b42f247bc2a7275b482e521f39..95e0e094425cedff2c8d0e98cb5cd6268735d680 100644 (file)
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -439,7 +439,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
                dict<SigBit, int> bit_user_cnt;
 
                for (auto wire : module->wires()) {
-                       if (wire->name[0] == '\\' && wire->attributes.count(ID::src))
+                       if (wire->name.isPublic() && wire->attributes.count(ID::src))
                                sigmap.add(wire);
                }
 
@@ -468,7 +468,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
                                }
 
                                if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
-                                       if (bit.wire->name[0] == '\\')
+                                       if (bit.wire->name.isPublic())
                                                sigmap.add(bit);
                                        continue;
                                }
@@ -493,7 +493,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
                                                entry.src.insert(s);
 
                                        SigBit bit = sigmap(conn.second[i]);
-                                       if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
+                                       if (bit.wire && bit.wire->name.isPublic() && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
                                                for (auto &s : bit.wire->get_strpool_attribute(ID::src))
                                                        entry.src.insert(s);
                                                entry.wire = bit.wire->name;

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index d7bf125d1556048e50c51fab4ae2a2b98d69591a..9fdac6147ea3a7691f9b8fab0e37e08f98bdef43 100644 (file)
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -1365,7 +1365,7 @@ struct SatPass : public Pass {
 
                if (show_public) {
                        for (auto wire : module->wires())
-                               if (wire->name[0] == '\\')
+                               if (wire->name.isPublic())
                                        shows.push_back(wire->name.str());
                }