Update doc for synth_xilinx

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 9178182fb0b57c005e73fcdd4c359b181f645f5e..10902a5606b7cad86ae25dc80d6e6f096f0b423f 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -113,19 +113,20 @@ struct SynthXilinxPass : public Pass
                log("        dffsr2dff\n");
                log("        dff2dffe\n");
                log("        opt -full\n");
-               log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
+               log("        techmap -map +/xilinx/arith_map.v\n");
                log("        opt -fast\n");
                log("\n");
-               log("    map_luts:\n");
-               log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
-               log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
-               log("        clean\n");
-               log("\n");
                log("    map_cells:\n");
                log("        techmap -map +/xilinx/cells_map.v\n");
+               log("        clean\n");
+               log("\n");
+               log("    map_luts:\n");
+               log("        techmap -map +/techmap.v\n");
+               log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
+               log("        clean\n");
+               log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v\n");
                log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
                log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
-               log("        clean\n");
                log("\n");
                log("    check:\n");
                log("        hierarchy -check\n");