rs6000.h (EXTRA_CONSTRAINT): Add 'a' for indexed or indirect address operand.

        * config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Add 'a' for indexed
        or indirect address operand.
        (EXTRA_ADDRESS_CONSTRAINT): New.
        * config/rs6000/rs6000.md (prefetch): Change constraint "p" to "a".

From-SVN: r103056

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 456967757d46ea4abd268edec5556d33d4d00e51..1058d983437e047768825397f67a905124297668 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2005-08-13  David Edelsohn  <edelsohn@gnu.org>
+
+       * config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Add 'a' for indexed
+       or indirect address operand.
+       (EXTRA_ADDRESS_CONSTRAINT): New.
+       * config/rs6000/rs6000.md (prefetch): Change constraint "p" to "a".
+
 2005-08-13  Sebastian Pop  <pop@cri.ensmp.fr>
 
        PR tree-optimization/22236

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 17c98c0699a1bf9aa1800b70c715b64abf39ac15..bab54a90309cb79d2ac2468f8b43f875d603d4c8 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1111,6 +1111,7 @@ enum reg_class
    'W' is a vector constant that can be easily generated (no mem refs).
    'Y' is an indexed or word-aligned displacement memory operand.
    'Z' is an indexed or indirect memory operand.
+   'a'  is an indexed or indirect address operand.
    't' is for AND masks that can be performed by two rldic{l,r} insns.  */
 
 #define EXTRA_CONSTRAINT(OP, C)                                                \
@@ -1127,6 +1128,7 @@ enum reg_class
    : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP)))           \
    : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP)))      \
    : (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP)))    \
+   : (C) == 'a' ? (indexed_or_indirect_address (OP, GET_MODE (OP)))    \
    : 0)
 
 /* Define which constraints are memory constraints.  Tell reload
@@ -1136,6 +1138,12 @@ enum reg_class
 #define EXTRA_MEMORY_CONSTRAINT(C, STR)                                \
   ((C) == 'Q' || (C) == 'Y' || (C) == 'Z')
 
+/* Define which constraints should be treated like address constraints
+   by the reload pass.  */
+
+#define EXTRA_ADDRESS_CONSTRAINT(C, STR)                       \
+  ((C) == 'a')
+
 /* Given an rtx X being reloaded into a reg required to be
    in class CLASS, return the class of reg to actually use.
    In general this is just CLASS; but on some machines

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 288b40f93b0ded8eb821a379113215d261148995..c873c8f6513a6f28c8218396af64fa2118d7985e 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14016,7 +14016,7 @@
 }")
 
 (define_insn "prefetch"
-  [(prefetch (match_operand 0 "indexed_or_indirect_address" "p")
+  [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
             (match_operand:SI 1 "const_int_operand" "n")
             (match_operand:SI 2 "const_int_operand" "n"))]
   "TARGET_POWERPC"