i965: Tell the shader compiler when we expect depth writes for gen6.

This fixes hangs in some Z-writes-in-shaders tests, though other
pieces don't come out correctly.

Bug #30392: hang in fbo-fblit-d24s8. (still fails with bad color drawn
to some targets)

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 7aad6caf719b50e4ee99a30263ac943eee819bb3..f2ce7565643600c3241646067fbc83795d2047d7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -318,6 +318,12 @@ static void brw_wm_populate_key( struct brw_context *brw,
       /* R31: MSAA position offsets. */
       /* R32-: bary for 32-pixel. */
       /* R58-59: interp W for 32-pixel. */
+
+      if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+        key->source_depth_to_render_target = GL_TRUE;
+        key->computes_depth = GL_TRUE;
+      }
+
    } else {
       brw_wm_lookup_iz(intel,
                       line_aa,