ARM: Squash state on FPSCR stride or len write.

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 961b9a3554b20eb55fadaf89b29fb8860a42bfa2..4911d50f1a356e3b5cf6d9b3ab683415221bfe57 100644 (file)
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -209,7 +209,8 @@ let {{
                                  { "code": vmsrFpscrCode,
                                    "predicate_test": predicateTest,
                                    "op_class": "SimdFloatMiscOp" },
-                                 ["IsSerializeAfter","IsNonSpeculative"])
+                                 ["IsSerializeAfter","IsNonSpeculative",
+                                  "IsSquashAfter"])
     header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
     decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
     exec_output += PredOpExecute.subst(vmsrFpscrIop);