soc/sdram: sync with new mibuild toolchain management

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index e9fbca1522dbbfcd292b51b32a8df97fc725b2bc..e6ecb9304c2e15b7380f8ec9c00a7ac152e58a8d 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -53,8 +53,8 @@ class SDRAMSoC(SoC):
                                # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
                                # Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
                                # Remove this workaround when fixed by Xilinx.
-                               from mibuild.xilinx.vivado import XilinxVivadoPlatform
-                               if isinstance(self.platform, XilinxVivadoPlatform):
+                               from mibuild.xilinx.vivado import XilinxVivadoToolchain
+                               if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
                                        from migen.fhdl.simplify import FullMemoryWE
                                        self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
                                else: