add what might turn out to be only what is needed to support mapreduce

scalar mode

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index b620d932d1cc4f08c6be10836aec11cdf000bb51..d0770862b633475a267c9ca696b93027401377c0 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -19,7 +19,8 @@ from openpower.exceptions import LDSTException
 from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder
 from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
 from openpower.decoder.power_svp64_rm import (SVP64RMModeDecode,
-                                              sv_input_record_layout)
+                                              sv_input_record_layout,
+                                              SVP64RMMode)
 from openpower.sv.svp64 import SVP64Rec
 
 from openpower.decoder.power_regspec_map import regspec_decode_read
@@ -1196,7 +1197,11 @@ class PowerDecode2(PowerDecodeSubset):
                                         crin_svdec, crin_svdec_b, crin_svdec_o])
             comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
             l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
-            comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
+            # in mapreduce mode, scalar out is *allowed*
+            with m.If(self.rm_dec.mode == SVP64RMMode.MAPREDUCE):
+                comb += self.no_out_vec.eq(0)
+            with m.Else():
+                comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
             # now create a general-purpose "test" as to whether looping
             # should continue.  this doesn't include predication bit-tests
             loop = self.loop_continue

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 00a57e827c0e3d5bb54c3d75a1599ac1d88dd492..ae153567b7d02ddf90541247afab4f4eba74e726 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -794,6 +794,9 @@ if __name__ == '__main__':
     lst = [
             "sv.stfsu/els 0.v, 16(4)",
     ]
+    lst = [
+             'sv.add./mr 5.v, 2.v, 1.v',
+    ]
     isa = SVP64Asm(lst)
     print ("list", list(isa))
     csvs = SVP64RM()