i965/vs: Add support for texel offsets.

The visit() half computes the values to put in the header based on the
IR and simply stuffs that in the vec4_instruction; the emit() half uses
this to set up the message header.  This works out well since emit() can
use brw_reg directly and access individual DWords without kludgery.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index d3505c3ba3dec36a6c10fbd9d2c9039a2892edc5..28da8c00628899b5ecc9a00d9e3c20030cea34d3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -271,6 +271,7 @@ public:
    int conditional_mod; /**< BRW_CONDITIONAL_* */
 
    int sampler;
+   uint32_t texture_offset; /**< Texture Offset bitfield */
    int target; /**< MRT target. */
    bool shadow_compare;
 

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index c131343c1558a3fced6efa2d4ac52325262e6a93..b2427da57e16764f637e74f2320b85a6854c12fe 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -418,7 +418,23 @@ vec4_visitor::generate_tex(vec4_instruction *inst,
 
    assert(msg_type != -1);
 
-   if (inst->header_present) {
+   /* Load the message header if present.  If there's a texture offset, we need
+    * to set it up explicitly and load the offset bitfield.  Otherwise, we can
+    * use an implied move from g0 to the first message register.
+    */
+   if (inst->texture_offset) {
+      /* Explicitly set up the message header by copying g0 to the MRF. */
+      brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
+                retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+
+      /* Then set the offset bits in DWord 2. */
+      brw_set_access_mode(p, BRW_ALIGN_1);
+      brw_MOV(p,
+             retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
+                    BRW_REGISTER_TYPE_UD),
+             brw_imm_uw(inst->texture_offset));
+      brw_set_access_mode(p, BRW_ALIGN_16);
+   } else if (inst->header_present) {
       /* Set up an implied move from g0 to the MRF. */
       src = brw_vec8_grf(0, 0);
    }

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index b49cf9c1fc37d825ddee9eac7adc2937b251c4ae..b424a0f22f75262da0060471a555557ee1e9a2a8 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1781,13 +1781,17 @@ vec4_visitor::visit(ir_texture *ir)
       assert(!"TXB is not valid for vertex shaders.");
    }
 
-   inst->header_present = intel->gen < 5;
+   /* Texel offsets go in the message header; Gen4 also requires headers. */
+   inst->header_present = ir->offset || intel->gen < 5;
    inst->base_mrf = 2;
    inst->mlen = inst->header_present + 1; /* always at least one */
    inst->sampler = sampler;
    inst->dst = dst_reg(this, glsl_type::get_instance(ir->type->base_type,4,1));
    inst->shadow_compare = ir->shadow_comparitor != NULL;
 
+   if (ir->offset != NULL)
+      inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
+
    /* MRF for the first parameter */
    int param_base = inst->base_mrf + inst->header_present;