re PR target/61948 ([ARM] [4.10 regression] ICE with DImode shift by 1 bit (in copypr...

PR target/61948

gcc/ChangeLog:
2014-07-29  Charles Baylis  <charles.baylis@linaro.org>

	PR target/61948
	* config/arm/neon.md (ashldi3_neon): Don't emit arm_ashldi3_1bit unless
	constraints are satisfied.
	(<shift>di3_neon): Likewise.

gcc/testsuite/ChangeLog:
2014-07-29  Charles Baylis  <charles.baylis@linaro.org>

        PR target/61948
        * gcc.target/arm/pr61948.c: New test case.

From-SVN: r213376

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f75f34682eb1ccea2a71234d5acfa35da3af085c..33930dce8298b31b172d06b222c34aa0615f447d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2014-07-31  Charles Baylis  <charles.baylis@linaro.org>
+
+       PR target/61948
+       * config/arm/neon.md (ashldi3_neon): Don't emit arm_ashldi3_1bit unless
+       constraints are satisfied.
+       (<shift>di3_neon): Likewise.
+
 2014-07-31  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/61964

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 1fc4dcd827585b857e192b1276008521c192c4a7..dc364eeb64e8cbb3b9a2eb5725338110ea3e8a7a 100644 (file)
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1041,7 +1041,9 @@
       }
     else
       {
-       if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
+       if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
+           && (!reg_overlap_mentioned_p (operands[0], operands[1])
+               || REGNO (operands[0]) == REGNO (operands[1])))
          /* This clobbers CC.  */
          emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
        else
@@ -1141,7 +1143,9 @@
       }
     else
       {
-       if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
+       if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
+           && (!reg_overlap_mentioned_p (operands[0], operands[1])
+               || REGNO (operands[0]) == REGNO (operands[1])))
          /* This clobbers CC.  */
          emit_insn (gen_arm_<shift>di3_1bit (operands[0], operands[1]));
        else

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1619d00dc815d835a6a17772a7c9817232cf06b4..1932ab146a55217a67024137302d35476042a67a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-07-31  Charles Baylis  <charles.baylis@linaro.org>
+
+       PR target/61948
+       * gcc.target/arm/pr61948.c: New test case.
+
 2014-07-31  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/61964

diff --git a/gcc/testsuite/gcc.target/arm/pr61948.c b/gcc/testsuite/gcc.target/arm/pr61948.c
new file mode 100644 (file)
index 0000000..411e898
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr61948.c
@@ -0,0 +1,16 @@
+/* PR target/61948 */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mthumb" } */
+/* { dg-add-options arm_neon } */
+
+long long f (long long *c)
+{
+  long long t = c[0];
+  asm ("nop" : : : "r0", "r3", "r4", "r5",
+                  "r6", "r7", "r8", "r9",
+                  "r10", "r11", "r12", "memory");
+  return t >> 1;
+}
+