voltage_domain =
VoltageDomain(voltage = '1V'))
+system.workload = SEWorkload()
+
# We are fine with 256 MB memory for now.
mem_range = AddrRange('256MB')
# Start address is 0
system = System(cpu = cpu_list,
mem_ranges = [AddrRange(options.mem_size)],
cache_line_size = options.cacheline_size,
- mem_mode = mem_mode)
+ mem_mode = mem_mode,
+ workload = SEWorkload())
if fast_forward:
system.future_cpu = future_cpu_list
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
(len(processes), args.num_cores))
sys.exit(1)
+ system.workload = SEWorkload()
+
# Assign one workload to each CPU
for cpu, workload in zip(system.cpu_cluster.cpus, processes):
cpu.workload = workload
options = parser.parse_args()
# create the system we are going to simulate
system = System()
+system.workload = SEWorkload()
# use timing mode for the interaction between master-slave ports
system.mem_mode = 'timing'
# set the clock fequency of the system
mem_mode = test_mem_mode,
mem_ranges = [AddrRange(options.mem_size)],
cache_line_size = options.cacheline_size,
- workload = NULL)
+ workload = SEWorkload())
if numThreads > 1:
system.multi_thread = True
binary = os.path.join(thispath, '../../../',
'tests/test-progs/hello/bin/', isa, 'linux/hello')
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
# Connect the system up to the membus
system.system_port = system.membus.slave
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
# Connect the system up to the membus
system.system_port = system.membus.slave
+system.workload = SEWorkload()
+
# Create a process for a simple "Hello World" application
process = Process()
# Set the command
binary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/',
isa, 'linux/threads')
+system.workload = SEWorkload()
+
# Create a process for a simple "multi-threaded" application
process = Process()
# Set the command
system.toL2bus = L2XBar(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
+system.workload = SEWorkload()
+
# ----------------------
# Connect the L2 cache and memory together
# ----------------------
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cpus, physmem = SimpleMemory(),
- membus = SystemXBar(clock = busFrequency))
+ membus = SystemXBar(clock = busFrequency),
+ workload = SEWorkload())
system.clock = '1GHz'
system.toL2bus = L2XBar(clock = busFrequency)
Source('root.cc')
Source('serialize.cc')
Source('drain.cc')
+Source('se_workload.cc')
Source('sim_events.cc')
Source('sim_object.cc')
Source('sub_system.cc')
work_cpus_ckpt_count = Param.Counter(0,
"create checkpoint when active cpu count value is reached")
- workload = Param.Workload(NULL, "Operating system kernel")
+ workload = Param.Workload(NULL, "Workload to run on this system")
init_param = Param.UInt64(0, "numerical value to pass into simulator")
readfile = Param.String("", "file to read startup script from")
symbolfile = Param.String("", "file to get the symbols from")
load_addr_offset = Param.UInt64(0, "Address to offset the kernel with")
command_line = Param.String("a", "boot flags to pass to the kernel")
+
+class SEWorkload(Workload):
+ type = 'SEWorkload'
+ cxx_header = "sim/se_workload.hh"
--- /dev/null
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sim/se_workload.hh"
+
+#include "params/SEWorkload.hh"
+
+SEWorkload::SEWorkload(const Params &p) : Workload(&p), _params(p)
+{
+}
+
+SEWorkload *
+SEWorkloadParams::create()
+{
+ return new SEWorkload(*this);
+}
--- /dev/null
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SIM_SE_WORKLOAD_HH__
+#define __SIM_SE_WORKLOAD_HH__
+
+#include "params/SEWorkload.hh"
+#include "sim/workload.hh"
+
+class SEWorkload : public Workload
+{
+ public:
+ using Params = SEWorkloadParams;
+
+ protected:
+ const Params &_params;
+
+ public:
+ const Params ¶ms() const { return _params; }
+
+ SEWorkload(const Params &p);
+
+ Addr
+ getEntry() const override
+ {
+ // This object represents the OS, not the individual processes running
+ // within it.
+ panic("No workload entry point for syscall emulation mode.");
+ }
+
+ Loader::Arch
+ getArch() const override
+ {
+ // ISA specific subclasses should implement this method.
+ // This implemenetation is just to avoid having to implement those for
+ // now, and will be removed in the future.
+ panic("SEWorkload::getArch() not implemented.");
+ }
+
+ const Loader::SymbolTable &
+ symtab(ThreadContext *) override
+ {
+ // This object represents the OS, not the individual processes running
+ // within it.
+ panic("No workload symbol table for syscall emulation mode.");
+ }
+
+ bool
+ insertSymbol(const Loader::Symbol &symbol) override
+ {
+ // This object represents the OS, not the individual processes running
+ // within it.
+ panic("No workload symbol table for syscall emulation mode.");
+ }
+};
+
+#endif // __SIM_SE_WORKLOAD_HH__
system = System(cpu = cpu_list,
mem_ranges = [AddrRange(options.mem_size)],
- mem_mode = 'timing')
+ mem_mode = 'timing',
+ workload = SEWorkload())
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system = System()
+system.workload = SEWorkload()
+
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
root = Root(full_system = False)
root.system = System()
+root.system.workload = SEWorkload()
+
root.system.clk_domain = SrcClockDomain()
root.system.clk_domain.clock = '3GHz'
root.system.clk_domain.voltage_domain = VoltageDomain()
projects / gem5.git / commitdiff