boards/targets/sim: get SDRAM working in simulation with sdram/model

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 5cd9d56cd19ab6fe47d11463b72ad2345c6fa0ff..0990ac6add91064de94ecf2696fd1e789c7eaa2a 100644 (file)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -7,18 +7,19 @@ from litex.gen import *
 from litex.boards.platforms import sim
 from litex.gen.genlib.io import CRG
 
-from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 from litex.soc.cores import uart
+from litex.soc.cores.sdram.settings import PhySettings, IS42S16160
+from litex.soc.cores.sdram.model import SDRAMPHYModel
 
 
-class BaseSoC(SoCCore):
+class BaseSoC(SoCSDRAM):
     def __init__(self, **kwargs):
         platform = sim.Platform()
-        SoCCore.__init__(self, platform,
+        SoCSDRAM.__init__(self, platform,
             clk_freq=int((1/(platform.default_clk_period))*1000000000),
             integrated_rom_size=0x8000,
-            integrated_main_ram_size=16*1024,
             with_uart=False,
             **kwargs)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
@@ -26,14 +27,33 @@ class BaseSoC(SoCCore):
         self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
         self.submodules.uart = uart.UART(self.uart_phy)
 
+        if not self.integrated_main_ram_size:
+            sdram_module = IS42S16160(self.clk_freq)
+            phy_settings = PhySettings(
+                memtype="SDR",
+                dfi_databits=1*16,
+                nphases=1,
+                rdphase=0,
+                wrphase=0,
+                rdcmdphase=0,
+                wrcmdphase=0,
+                cl=2,
+                read_latency=4,
+                write_latency=0
+            )
+            self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
+            self.register_sdram(self.sdrphy, "minicon",
+                                sdram_module.geom_settings, sdram_module.timing_settings)
+
+
 
 def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
     builder_args(parser)
-    soc_core_args(parser)
+    soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(**soc_core_argdict(args))
+    soc = BaseSoC(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 

diff --git a/litex/build/xilinx/__init__.py b/litex/build/xilinx/__init__.py
index 53e6e840ae6dfcbb71a6f4d00d916e113a8d594c..00e3072580837d4d546649ad7a372aa6355f0f30 100644 (file)
--- a/litex/build/xilinx/__init__.py
+++ b/litex/build/xilinx/__init__.py
@@ -1,2 +1,2 @@
 from litex.build.xilinx.platform import XilinxPlatform
-from litex.build.xilinx.programmer import UrJTAG, XC3SProg, FpgaProg, VivadoProgrammer, iMPACT, Adept
+from litex.build.xilinx.programmer import XC3SProg, FpgaProg, VivadoProgrammer, iMPACT

diff --git a/litex/soc/cores/sdram/model.py b/litex/soc/cores/sdram/model.py
index a04b09802d1c72ce496f397134c8cff3760c0a64..a8792250ae8308bf8c05ef8f46aff38d3be6ba44 100644 (file)
--- a/litex/soc/cores/sdram/model.py
+++ b/litex/soc/cores/sdram/model.py
@@ -8,8 +8,10 @@
 
 from litex.gen import *
 from litex.gen.fhdl.specials import *
-from litex.soc.mem.sdram.phy.dfi import *
-from litex.soc.mem import sdram
+from litex.soc.interconnect.dfi import *
+
+from functools import reduce
+from operator import or_
 
 
 class Bank(Module):
@@ -27,7 +29,8 @@ class Bank(Module):
         self.read_col = Signal(max=ncols)
         self.read_data = Signal(data_width)
 
-        ###
+        # # #
+
         active = Signal()
         row = Signal(max=nrows)
 
@@ -74,7 +77,8 @@ class DFIPhase(Module):
         self.write = Signal()
         self.read = Signal()
 
-        ###
+        # # #
+
         self.comb += [
             If(~phase.cs_n & ~phase.ras_n & phase.cas_n,
                 self.activate.eq(phase.we_n),
@@ -87,7 +91,7 @@ class DFIPhase(Module):
         ]
 
 
-class SDRAMPHYSim(Module):
+class SDRAMPHYModel(Module):
     def __init__(self, module, settings):
         if settings.memtype in ["SDR"]:
             burst_length = settings.nphases*1  # command multiplication*SDR
@@ -104,7 +108,8 @@ class SDRAMPHYSim(Module):
 
         self.dfi = Interface(addressbits, bankbits, self.settings.dfi_databits, self.settings.nphases)
 
-        ###
+        # # #
+
         nbanks = 2**bankbits
         nrows = 2**rowbits
         ncols = 2**colbits
@@ -171,9 +176,10 @@ class SDRAMPHYSim(Module):
         banks_read = Signal()
         banks_read_data = Signal(data_width)
         self.comb += [
-            banks_read.eq(optree("|", [bank.read for bank in banks])),
-            banks_read_data.eq(optree("|", [bank.read_data for bank in banks]))
+            banks_read.eq(reduce(or_, [bank.read for bank in banks])),
+            banks_read_data.eq(reduce(or_, [bank.read_data for bank in banks]))
         ]
+
         # simulate read latency
         for i in range(self.settings.read_latency):
             new_banks_read = Signal()

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index bb917df6e039e1499408d81355b84f731a522302..75421a39c06f051afb4c15b5676fdcc4d8ad2c47 100644 (file)
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -423,7 +423,7 @@ int sdrlevel(void)
 
 #endif /* CSR_DDRPHY_BASE */
 
-#define TEST_DATA_SIZE (2*1024*1024)
+#define TEST_DATA_SIZE (32*1024) // FIXME add #define
 #define TEST_DATA_RANDOM 1
 
 #define TEST_ADDR_SIZE (32*1024)