yield GPR(r[index])
+@final
+@plain_data(unsafe_hash=True, frozen=True)
+class EqualityConstraint:
+ __slots__ = "lhs", "rhs"
+
+ def __init__(self, lhs, rhs):
+ # type: (SSAVal, SSAVal) -> None
+ self.lhs = lhs
+ self.rhs = rhs
+
+
@plain_data(unsafe_hash=True, frozen=True)
class Op(metaclass=ABCMeta):
__slots__ = ()
# type: (SSAVal, dict[SSAVal, PhysLoc]) -> Iterable[PhysLoc]
...
+ def get_equality_constraints(self):
+ # type: () -> Iterable[EqualityConstraint]
+ if False:
+ yield ...
+
def __init__(self):
pass
else:
yield from self.RB.possible_reg_assignments(val, value_assignments)
+ def get_equality_constraints(self):
+ # type: () -> Iterable[EqualityConstraint]
+ yield EqualityConstraint(self.CY_in, self.CY_out)
+
def to_reg_set(v):
# type: (None | GPR | range) -> set[GPR]
val, value_assignments,
conflicting_regs=to_reg_set(RT_range) | to_reg_set(RC_RS_reg))
+ def get_equality_constraints(self):
+ # type: () -> Iterable[EqualityConstraint]
+ yield EqualityConstraint(self.RC, self.RS)
+
@final
@unique
else:
yield from self.RS.possible_reg_assignments(value_assignments)
+ def get_equality_constraints(self):
+ # type: () -> Iterable[EqualityConstraint]
+ yield EqualityConstraint(self.mem_in, self.mem_out)
+
@plain_data(unsafe_hash=True, frozen=True)
@final