/*
- * Copyright (c) 2011-2013,2017-2018 ARM Limited
+ * Copyright (c) 2011-2013,2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
*/
#include "arch/arm/insts/misc64.hh"
+#include "arch/arm/isa.hh"
std::string
ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
break;
case MISCREG_IMPDEF_UNIMPL:
trap_to_hyp = hcr.tidcp && el == EL1;
+ // GICv3 regs
+ case MISCREG_ICC_SGI0R_EL1:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trap_to_hyp = hcr.fmo && el == EL1;
+ break;
+ case MISCREG_ICC_SGI1R_EL1:
+ case MISCREG_ICC_ASGI1R_EL1:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trap_to_hyp = hcr.imo && el == EL1;
+ break;
default:
break;
}
/*
- * Copyright (c) 2009-2014, 2016-2018 ARM Limited
+ * Copyright (c) 2009-2014, 2016-2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
case MISCREG_PMCR:
trapToHype = hdcr.tpmcr;
break;
+ // GICv3 regs
+ case MISCREG_ICC_SGI0R:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trapToHype = hcr.fmo;
+ break;
+ case MISCREG_ICC_SGI1R:
+ case MISCREG_ICC_ASGI1R:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trapToHype = hcr.imo;
+ break;
// No default action needed
default:
break;