Fix "a" extension

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 7e674cb871a8ce23e4a17ad1b562f7d712b9fc3c..3d275214bfd1ebd43647e64c15937c0e57356b88 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -681,9 +681,12 @@ struct XAigerWriter
                        for (auto cell : box_list) {
                                RTLIL::Module* box_module = module->design->module(cell->type);
                                int box_inputs = 0, box_outputs = 0;
-                               Cell *holes_cell = holes_module->addCell(cell->name, cell->type);
+                               Cell *holes_cell = nullptr;
+                               if (box_module->get_bool_attribute("\\whitebox"))
+                                       holes_cell = holes_module->addCell(cell->name, cell->type);
 
                                RTLIL::Wire *holes_wire;
+                               // TODO: Only sort once
                                box_module->wires_.sort(RTLIL::sort_by_id_str());
                                for (const auto w : box_module->wires()) {
                                        RTLIL::SigSpec port_wire;
@@ -695,9 +698,11 @@ struct XAigerWriter
                                                                holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
                                                                holes_wire->port_input = true;
                                                        }
-                                                       port_wire.append(holes_wire);
+                                                       if (holes_cell)
+                                                               port_wire.append(holes_wire);
                                                }
-                                               holes_cell->setPort(w->name, port_wire);
+                                               if (!port_wire.empty())
+                                                       holes_cell->setPort(w->name, port_wire);
                                        }
                                        if (w->port_output) {
                                                box_outputs += GetSize(w);
@@ -707,9 +712,13 @@ struct XAigerWriter
                                                        else
                                                                holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
                                                        holes_wire->port_output = true;
-                                                       port_wire.append(holes_wire);
+                                                       if (holes_cell)
+                                                               port_wire.append(holes_wire);
+                                                       else
+                                                               holes_module->connect(holes_wire, RTLIL::S0);
                                                }
-                                               holes_cell->setPort(w->name, port_wire);
+                                               if (!port_wire.empty())
+                                                       holes_cell->setPort(w->name, port_wire);
                                        }
                                }
 
@@ -741,12 +750,13 @@ struct XAigerWriter
                                //       each box type once...
                                Pass::call(holes_module->design, "opt_merge -share_all");
 
-                               Pass::call(holes_module->design, "flatten -wb;");
+                               Pass::call(holes_module->design, "flatten -wb");
 
                                // TODO: Should techmap all lib_whitebox-es once
-                               Pass::call(holes_module->design, "techmap;");
+                               //Pass::call(holes_module->design, "techmap");
 
-                               Pass::call(holes_module->design, "aigmap; clean -purge");
+                               Pass::call(holes_module->design, "aigmap");
+                               Pass::call(holes_module->design, "clean -purge");
 
                                holes_module->design->selection_stack.pop_back();
 

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 9f3d2287b732da76f44caa223a5a10fed8fed4b6..3c01321357e35eddfc40c4d8b02c458ed0a51ee1 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -25,7 +25,9 @@
 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
-#define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m"
+//#define ABC_COMMAND_LUT "&st; &sweep -v; &ps -l -m; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m"
+#define ABC_COMMAND_LUT "&st; "/*"&sweep; "*/"&scorr; "/*"dc2; "*/"&retime; &dch -f; &ps -l -m; &if; &ps -l -m"
+//#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m"
 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"