(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 8d144e51094bc4240d6f3dda1941385c681abf66..bb333141f9ceb6a2af9f3299e7b236c3355cb2d3 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -91,8 +91,6 @@ Pages being developed and examples
   contains explanations and further details
 * [[sv/svp64_quirks]] things in SVP64  that slightly break the rules
 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
-* [[sv/vector_comparative_analysis]] - a list of Packed SIMD, GPU,
-  and other Scalable Vector ISAs
 * [[sv/sprs]] SPRs
 * SVP64 "Modes":
   - For condition register operations see [[sv/cr_ops]] - SVP64 Condition
@@ -173,9 +171,10 @@ Examples experiments future ideas discussion:
 Additional links:
 
 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
+* [[sv/vector_isa_comparison]] - a list of Packed SIMD, GPU,
+  and other Scalable Vector ISAs
 * [[simple_v_extension]] old (deprecated) version
 * [[openpower/sv/llvm]]
-* [[openpower/sv/effect-of-more-decode-stages-on-reg-renaming]]
 
 # Major opcodes summary