configs: MemConfig, add QoSMemSinkCtrl support

QoSMemSinkInterface is a special case of memory interface type, similar
to SimpleMemory. It requires a QoSMemSinkCtrl where most model parameters
are exposed. By adding support in "config_mem", we allow configurations
with multiple QoSMemSinkCtrls to be centrally configured, particularly
interleaving parameters.

Change-Id: I46462b55d587acd2c861963bc0279bce92d5f450
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35797
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 8221f85f001e530ad5c0b0453a75a3ac7e18b643..63301abca2e5f605f15d4b65a2bd0e810f6f3d64 100644 (file)
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -229,11 +229,15 @@ def config_mem(options, system):
                                              static_frontend_latency = '4ns')
                 elif opt_mem_type == "SimpleMemory":
                     mem_ctrl = m5.objects.SimpleMemory()
+                elif opt_mem_type == "QoSMemSinkInterface":
+                    mem_ctrl = m5.objects.QoSMemSinkCtrl()
                 else:
                     mem_ctrl = m5.objects.MemCtrl()
 
                 # Hookup the controller to the interface and add to the list
-                if opt_mem_type != "SimpleMemory":
+                if opt_mem_type == "QoSMemSinkInterface":
+                    mem_ctrl.interface = dram_intf
+                elif opt_mem_type != "SimpleMemory":
                     mem_ctrl.dram = dram_intf
 
                 mem_ctrls.append(mem_ctrl)