l3pt[SCRATCH / RISCV_PGSIZE] = ((uintptr_t)scratch >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_A | PTE_D | PTE_V | PTE_R | PTE_W;
#if __riscv_xlen == 64
l2pt[0] = ((uintptr_t)l3pt >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
- uintptr_t vm_choice = SPTBR_MODE_SV39;
+ uintptr_t vm_choice = SATP_MODE_SV39;
#else
- uintptr_t vm_choice = SPTBR_MODE_SV32;
+ uintptr_t vm_choice = SATP_MODE_SV32;
#endif
write_csr(sptbr, ((uintptr_t)l1pt >> RISCV_PGSHIFT) |
- (vm_choice * (SPTBR_MODE & ~(SPTBR_MODE<<1))));
+ (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
write_csr(pmpcfg0, (PMP_NAPOT | PMP_R) << 16);
write_csr(pmpaddr2, -1);
}
# Set up a page table entry that maps 0x0... to 0x8...
la t0, page_table
srli t0, t0, PGSHIFT
- csrw CSR_SPTBR, t0
+ csrw CSR_SATP, t0
# update mstatus
csrr t1, CSR_MSTATUS
#if XLEN == 32
- li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV32 << 24))
+ li t0, (MSTATUS_MPRV | (SATP_MODE_SV32 << 24))
#else
- li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV39 << 24))
+ li t0, (MSTATUS_MPRV | (SATP_MODE_SV39 << 24))
#endif
#li t0, ((VM_SV39 << 24))
or t1, t0, t1
-Subproject commit db0bfa223142e56b17dae6d92610f195014bbb80
+Subproject commit 68cad7baf3ed0a4553fffd14726d24519ee1296a
#undef RVTEST_RV64M
#define RVTEST_RV64M RVTEST_RV32M
-#undef SPTBR_MODE_SV39
-#define SPTBR_MODE_SV39 SPTBR_MODE_SV32
+#undef SATP_MODE_SV39
+#define SATP_MODE_SV39 SATP_MODE_SV32
#include "../rv64si/dirty.S"
RVTEST_CODE_BEGIN
# Turn on VM
- li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
+ li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0