top: integrate ADC for pots

diff --git a/milkymist/adc/__init__.py b/milkymist/adc/__init__.py
deleted file mode 100644 (file)
index b785ee0..0000000
--- a/milkymist/adc/__init__.py
+++ /dev/null
@@ -1,60 +0,0 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
-from migen.bank.description import *
-from migen.genlib.misc import optree
-from migen.genlib.cdc import MultiReg
-
-class CounterADC(Module, AutoCSR):
-       def __init__(self, charge, sense, width=24):
-               if not isinstance(sense, collections.Iterable):
-                       sense = [sense]
-
-               channels = len(sense)
-
-               self._start_busy = CSR()
-               self._overflow = CSRStatus(channels)
-               self._polarity = CSRStorage()
-
-               count = Signal(width)
-               busy = Signal(channels)
-
-               res = []
-               for i in range(channels):
-                       res.append(CSRStatus(width, name="res"+str(i)))
-                       setattr(self, "_res"+str(i), res[-1])
-
-               any_busy = Signal()
-               self.comb += [
-                       any_busy.eq(optree("|",
-                           [busy[i] for i in range(channels)])),
-                       self._start_busy.w.eq(any_busy)
-               ]
-
-               carry = Signal()
-
-               self.sync += [
-                       If(self._start_busy.re,
-                               count.eq(0),
-                               busy.eq((1 << channels)-1),
-                               self._overflow.status.eq(0),
-                               charge.eq(~self._polarity.storage)
-                       ).Elif(any_busy,
-                               Cat(count, carry).eq(count + 1),
-                               If(carry,
-                                       self._overflow.status.eq(busy),
-                                       busy.eq(0)
-                               )
-                       ).Else(
-                               charge.eq(self._polarity.storage)
-                       )
-               ]
-
-               for i in range(channels):
-                       sense_synced = Signal()
-                       self.specials += MultiReg(sense[i], sense_synced)
-                       self.sync += If(busy[i],
-                               If(sense_synced != self._polarity.storage,
-                                       res[i].status.eq(count),
-                                       busy[i].eq(0)
-                               )
-                       )

diff --git a/milkymist/counteradc/__init__.py b/milkymist/counteradc/__init__.py
new file mode 100644 (file)
index 0000000..b785ee0
--- /dev/null
+++ b/milkymist/counteradc/__init__.py
@@ -0,0 +1,60 @@
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+from migen.bank.description import *
+from migen.genlib.misc import optree
+from migen.genlib.cdc import MultiReg
+
+class CounterADC(Module, AutoCSR):
+       def __init__(self, charge, sense, width=24):
+               if not isinstance(sense, collections.Iterable):
+                       sense = [sense]
+
+               channels = len(sense)
+
+               self._start_busy = CSR()
+               self._overflow = CSRStatus(channels)
+               self._polarity = CSRStorage()
+
+               count = Signal(width)
+               busy = Signal(channels)
+
+               res = []
+               for i in range(channels):
+                       res.append(CSRStatus(width, name="res"+str(i)))
+                       setattr(self, "_res"+str(i), res[-1])
+
+               any_busy = Signal()
+               self.comb += [
+                       any_busy.eq(optree("|",
+                           [busy[i] for i in range(channels)])),
+                       self._start_busy.w.eq(any_busy)
+               ]
+
+               carry = Signal()
+
+               self.sync += [
+                       If(self._start_busy.re,
+                               count.eq(0),
+                               busy.eq((1 << channels)-1),
+                               self._overflow.status.eq(0),
+                               charge.eq(~self._polarity.storage)
+                       ).Elif(any_busy,
+                               Cat(count, carry).eq(count + 1),
+                               If(carry,
+                                       self._overflow.status.eq(busy),
+                                       busy.eq(0)
+                               )
+                       ).Else(
+                               charge.eq(self._polarity.storage)
+                       )
+               ]
+
+               for i in range(channels):
+                       sense_synced = Signal()
+                       self.specials += MultiReg(sense[i], sense_synced)
+                       self.sync += If(busy[i],
+                               If(sense_synced != self._polarity.storage,
+                                       res[i].status.eq(count),
+                                       busy[i].eq(0)
+                               )
+                       )

diff --git a/top.py b/top.py
index 029a02fd0dca23c79a29535d20ffa82161939bff..4b8c4b8736c5f4b4e43e389b3f0855455e293f42 100644 (file)
--- a/top.py
+++ b/top.py
@@ -8,7 +8,7 @@ from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
 from migen.bank import csrgen
 
 from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
-       identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler
+       identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler, counteradc
 from cif import get_macros
 
 version = get_macros("common/version.h")["VERSION"][1:-1]
@@ -77,6 +77,7 @@ class SoC(Module):
                "dvisampler0_edid_mem": 9,
                "dvisampler1":                  10,
                "dvisampler1_edid_mem": 11,
+               "pots":                                 12,
        }
 
        interrupt_map = {
@@ -148,6 +149,9 @@ class SoC(Module):
                self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
                self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), asmiport_dvi0)
                self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), asmiport_dvi1)
+               pots_pads = platform.request("dvi_pots")
+               self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
+                       [pots_pads.blackout, pots_pads.crossfade])
 
                self.submodules.csrbankarray = csrgen.BankArray(self,
                        lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])