dont do polymorphic rgbttl for now

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index db1b47967a8d4d0b794f4613e4b317cf694a7581..4e7e3f92401eee58a0331180d1a51985c727b890 100644 (file)
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -29,6 +29,7 @@ Details:
 --------------------------------------------------------------------------------------------------
 */
 package rgbttl_dummy;
+  `define RGBTTL_WIDTH
   `include "instance_defines.bsv"
   import ClockDiv::*;
   import ConcatReg::*;
@@ -36,19 +37,17 @@ package rgbttl_dummy;
   import BUtils ::*;
   import AXI4_Lite_Types::*;
 
-  interface Ifc_rgbttl_dummy#(numeric type buswidth);
+  interface Ifc_rgbttl_dummy();
          interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
     method  Bit#(1) de; 
     method  Bit#(1) ck;
     method  Bit#(1) vs;
     method  Bit#(1) hs;
-    method  Bit#(buswidth) data;
+    method  Bit#(`RGBTTL_WIDTH) data;
   endinterface
 
   (*synthesize*)
-  module mkrgbttl_dummy(Ifc_rgbttl_dummy#(buswidth))
-        provisos(
-        );
+  module mkrgbttl_dummy(Ifc_rgbttl_dummy)
                AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
                             s_xactor<-mkAXI4_Lite_Slave_Xactor();
       let v_buswidth = valueOf(v_buswidth);
@@ -57,8 +56,8 @@ package rgbttl_dummy;
       Reg#(Bit#(1)) rg_ck <- mkReg(0);
       Reg#(Bit#(1)) rg_vs <- mkReg(0);
       Reg#(Bit#(1)) rg_hs <- mkReg(0);
-      Reg#(Bit#(v_buswidth)) rg_data;
-      for(Integer i = 0; i < v_no_of_ir_pins;i=i+1) begin
+      Reg#(Bit#(`RGBTTL_WIDTH)) rg_data;
+      for(Integer i = 0; i < `RGBTTL_WIDTH;i=i+1) begin
         rg_data[i] <- mkReg(0);
       end