arguments.hh
faults.hh
interrupts.hh
+ isa.hh
isa_traits.hh
kernel_stats.hh
locked_mem.hh
Source('floatregfile.cc')
Source('intregfile.cc')
Source('ipr.cc')
+ Source('isa.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
Source('regfile.cc')
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/alpha/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace AlphaISA
+{
+
+void
+ISA::clear()
+{
+ miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+ return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+ return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+ miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+ miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+ miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ miscRegFile.unserialize(cp, section);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ALPHA_ISA_HH__
+#define __ARCH_ALPHA_ISA_HH__
+
+#include "arch/alpha/miscregfile.hh"
+#include "arch/alpha/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace AlphaISA
+{
+ class ISA
+ {
+ protected:
+ MiscRegFile miscRegFile;
+
+ public:
+
+ void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+ {
+ miscRegFile.expandForMultithreading(num_threads, num_vpes);
+ }
+
+ void reset(std::string core_name, ThreadID num_threads,
+ unsigned num_vpes, BaseCPU *_cpu)
+ {
+ miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+ }
+
+ int instAsid()
+ {
+ return miscRegFile.getInstAsid();
+ }
+
+ int dataAsid()
+ {
+ return miscRegFile.getDataAsid();
+ }
+
+ void clear();
+
+ MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+ void setMiscRegNoEffect(int miscReg, const MiscReg val);
+ void setMiscReg(int miscReg, const MiscReg val,
+ ThreadContext *tc);
+
+ int
+ flattenIntIndex(int reg)
+ {
+ return reg;
+ }
+
+ int
+ flattenFloatIndex(int reg)
+ {
+ return reg;
+ }
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+
+ ISA()
+ {
+ clear();
+ }
+ };
+}
+
+#endif
output decoder {{
#include <cmath>
+#include "arch/alpha/miscregfile.hh"
#include "base/cprintf.hh"
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
#include "sim/pseudo_inst.hh"
#include "arch/alpha/ipr.hh"
+#include "arch/alpha/miscregfile.hh"
#include "base/fenv.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/base.hh"
*/
#include "arch/alpha/regfile.hh"
+#include "arch/alpha/miscregfile.hh"
#include "cpu/thread_context.hh"
using namespace std;
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
- miscRegFile.serialize(os);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
- miscRegFile.unserialize(cp, section);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
protected:
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
public:
#if FULL_SYSTEM
int intrflag; // interrupt flag
-
- int
- instAsid()
- {
- return miscRegFile.getInstAsid();
- }
-
- int
- dataAsid()
- {
- return miscRegFile.getDataAsid();
- }
#endif // FULL_SYSTEM
void
{
intRegFile.clear();
floatRegFile.clear();
- miscRegFile.clear();
- }
-
- MiscReg
- readMiscRegNoEffect(int miscReg)
- {
- return miscRegFile.readRegNoEffect(miscReg);
- }
-
- MiscReg
- readMiscReg(int miscReg, ThreadContext *tc)
- {
- return miscRegFile.readReg(miscReg, tc);
- }
-
- void
- setMiscRegNoEffect(int miscReg, const MiscReg &val)
- {
- miscRegFile.setRegNoEffect(miscReg, val);
- }
-
- void
- setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
- {
- miscRegFile.setReg(miscReg, val, tc);
}
FloatReg
const std::string §ion);
};
-static inline int
-flattenIntIndex(ThreadContext * tc, int reg)
-{
- return reg;
-}
-
-static inline int
-flattenFloatIndex(ThreadContext * tc, int reg)
-{
- return reg;
-}
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
Source('insts/mem.cc')
Source('insts/pred_inst.cc')
Source('insts/static_inst.cc')
+ Source('isa.cc')
Source('pagetable.cc')
Source('regfile/regfile.cc')
Source('tlb.cc')
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/arm/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace ArmISA
+{
+
+void
+ISA::clear()
+{
+ miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+ return miscRegFile.readRegNoEffect(miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+ return miscRegFile.readReg(miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+ miscRegFile.setRegNoEffect(miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+ miscRegFile.setReg(miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+ //miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ //miscRegFile.unserialize(cp, section);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ARM_ISA_HH__
+#define __ARCH_MRM_ISA_HH__
+
+#include "arch/arm/regfile/misc_regfile.hh"
+#include "arch/arm/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace ArmISA
+{
+ class ISA
+ {
+ protected:
+ MiscRegFile miscRegFile;
+
+ public:
+ void clear();
+
+ MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+ void setMiscRegNoEffect(int miscReg, const MiscReg val);
+ void setMiscReg(int miscReg, const MiscReg val,
+ ThreadContext *tc);
+
+ int
+ flattenIntIndex(int reg)
+ {
+ return reg;
+ }
+
+ int
+ flattenFloatIndex(int reg)
+ {
+ return reg;
+ }
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+
+ ISA()
+ {
+ clear();
+ }
+ };
+}
+
+#endif
#ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
#define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
+#include "arch/arm/isa_traits.hh"
#include "arch/arm/types.hh"
#include "sim/faults.hh"
{
intRegFile.serialize(os);
//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
- //SERIALZE_ARRAY(miscRegFile);
- //SERIALIZE_SCALAR(miscRegs.fpcr);
- //SERIALIZE_SCALAR(miscRegs.lock_flag);
- //SERIALIZE_SCALAR(miscRegs.lock_addr);
- //SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
}
{
intRegFile.unserialize(cp, section);
//UNSERIALIZE_ARRAY(floatRegFile);
- //UNSERIALZE_ARRAY(miscRegFile);
- //UNSERIALIZE_SCALAR(miscRegs.fpcr);
- //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
- //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
- //UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
-
}
} // namespace ArmISA
protected:
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
public:
{
intRegFile.clear();
floatRegFile.clear();
- miscRegFile.clear();
- }
-
- MiscReg readMiscRegNoEffect(int miscReg)
- {
- return miscRegFile.readRegNoEffect(miscReg);
- }
-
- MiscReg readMiscReg(int miscReg, ThreadContext *tc)
- {
- return miscRegFile.readReg(miscReg, tc);
- }
-
- void setMiscRegNoEffect(int miscReg, const MiscReg &val)
- {
- miscRegFile.setRegNoEffect(miscReg, val);
- }
-
- void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc)
- {
- miscRegFile.setReg(miscReg, val, tc);
}
FloatRegVal readFloatReg(int floatReg)
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string §ion);
-
- void changeContext(RegContextParam param, RegContextVal val)
- {
- }
};
- static inline int flattenIntIndex(ThreadContext * tc, int reg)
- {
- return reg;
- }
-
- static inline int flattenFloatIndex(ThreadContext * tc, int reg)
- {
- return reg;
- }
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
if env['TARGET_ISA'] == 'mips':
Source('faults.cc')
+ Source('isa.cc')
Source('regfile/int_regfile.cc')
Source('regfile/float_regfile.cc')
Source('regfile/misc_regfile.cc')
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/mips/isa.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "cpu/thread_context.hh"
+
+namespace MipsISA
+{
+
+void
+ISA::clear()
+{
+ miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+ return miscRegFile.readRegNoEffect(miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+ return miscRegFile.readReg(miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+ miscRegFile.setRegNoEffect(miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+ miscRegFile.setReg(miscReg, val, tc);
+}
+
+void
+ISA::serialize(std::ostream &os)
+{
+ //miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ //miscRegFile.unserialize(cp, section);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_MIPS_ISA_HH__
+#define __ARCH_MIPS_ISA_HH__
+
+#include "arch/mips/regfile/misc_regfile.hh"
+#include "arch/mips/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace MipsISA
+{
+ class ISA
+ {
+ protected:
+ MiscRegFile miscRegFile;
+
+ public:
+
+ void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+ {
+ miscRegFile.expandForMultithreading(num_threads, num_vpes);
+ }
+
+ void reset(std::string core_name, ThreadID num_threads,
+ unsigned num_vpes, BaseCPU *_cpu)
+ {
+ miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
+ }
+
+ int instAsid()
+ {
+ return miscRegFile.getInstAsid();
+ }
+
+ int dataAsid()
+ {
+ return miscRegFile.getDataAsid();
+ }
+
+ void clear();
+
+ MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+ void setMiscRegNoEffect(int miscReg, const MiscReg val);
+ void setMiscReg(int miscReg, const MiscReg val,
+ ThreadContext *tc);
+
+ int
+ flattenIntIndex(int reg)
+ {
+ return reg;
+ }
+
+ int
+ flattenFloatIndex(int reg)
+ {
+ return reg;
+ }
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+
+ ISA()
+ {
+ clear();
+ }
+ };
+}
+
+#endif
}
-static inline int flattenIntIndex(ThreadContext * tc, int reg)
-{
- return reg;
-}
-
void
MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
{
{
intRegFile.clear();
floatRegFile.clear();
- miscRegFile.clear();
}
void
{
bzero(&intRegFile, sizeof(intRegFile));
bzero(&floatRegFile, sizeof(floatRegFile));
- miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
}
IntReg
return intRegFile.setReg(intReg, val);
}
-MiscReg
-RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid)
-{
- return miscRegFile.readRegNoEffect(miscReg, tid);
-}
-
-MiscReg
-RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid)
-{
- return miscRegFile.readReg(miscReg, tc, tid);
-}
-
-void
-RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid)
-{
- miscRegFile.setRegNoEffect(miscReg, val, tid);
-}
-
-void
-RegFile::setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid)
-{
- miscRegFile.setReg(miscReg, val, tc, tid);
-}
-
FloatRegVal
RegFile::readFloatReg(int floatReg)
{
intRegFile.setShadowSet(css);
}
-int
-RegFile::instAsid()
-{
- return miscRegFile.getInstAsid();
-}
-
-int
-RegFile::dataAsid()
-{
- return miscRegFile.getDataAsid();
-}
Addr
RegFile::readPC()
{
intRegFile.serialize(os);
//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
- //SERIALZE_ARRAY(miscRegFile);
- //SERIALIZE_SCALAR(miscRegs.fpcr);
- //SERIALIZE_SCALAR(miscRegs.lock_flag);
- //SERIALIZE_SCALAR(miscRegs.lock_addr);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
{
intRegFile.unserialize(cp, section);
//UNSERIALIZE_ARRAY(floatRegFile);
- //UNSERIALZE_ARRAY(miscRegFile);
- //UNSERIALIZE_SCALAR(miscRegs.fpcr);
- //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
- //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
-
}
} // namespace MipsISA
//#include "arch/mips/mt.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
-#include "arch/mips/regfile/misc_regfile.hh"
//#include "cpu/base.hh"
#include "sim/faults.hh"
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
public:
void clear();
void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu);
- MiscRegFile *getMiscRegFilePtr();
IntReg readIntReg(int intReg);
Fault setIntReg(int intReg, const IntReg &val);
- MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0);
- MiscReg readMiscReg(int miscReg, ThreadContext *tc,
- ThreadID tid = 0);
- void setMiscRegNoEffect(int miscReg, const MiscReg &val,
- ThreadID tid = 0);
- void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid = 0);
-
FloatRegVal readFloatReg(int floatReg);
FloatRegVal readFloatReg(int floatReg, int width);
FloatRegBits readFloatRegBits(int floatReg);
void setShadowSet(int css);
- int instAsid();
- int dataAsid();
-
public:
Addr readPC();
void setPC(Addr val);
//
// Register File Utility Functions
//
- static inline int flattenFloatIndex(ThreadContext * tc, int reg)
- {
- return reg;
- }
-
- static inline int flattenIntIndex(ThreadContext * tc, int reg)
- {
- // Implement Shadow Sets Stuff Here;
- return reg;
- }
-
static inline MachInst makeRegisterCopy(int dest, int src) {
panic("makeRegisterCopy not implemented");
return 0;
Source('faults.cc')
Source('floatregfile.cc')
Source('intregfile.cc')
+ Source('isa.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
Source('regfile.cc')
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/sparc/isa.hh"
+#include "cpu/thread_context.hh"
+
+namespace SparcISA
+{
+
+void
+ISA::clear()
+{
+ miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+ return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+ return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+ miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+ miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+int
+ISA::flattenIntIndex(int reg)
+{
+ int gl = miscRegFile.readRegNoEffect(MISCREG_GL);
+ int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP);
+ //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
+ int newReg;
+ //The total number of global registers
+ int numGlobals = (MaxGL + 1) * 8;
+ if(reg < 8)
+ {
+ //Global register
+ //Put it in the appropriate set of globals
+ newReg = reg + gl * 8;
+ }
+ else if(reg < NumIntArchRegs)
+ {
+ //Regular windowed register
+ //Put it in the window pointed to by cwp
+ newReg = numGlobals +
+ ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
+ }
+ else if(reg < NumIntArchRegs + NumMicroIntRegs)
+ {
+ //Microcode register
+ //Displace from the end of the regular registers
+ newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
+ }
+ else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
+ {
+ reg -= (NumIntArchRegs + NumMicroIntRegs);
+ if(reg < 8)
+ {
+ //Global register from the next window
+ //Put it in the appropriate set of globals
+ newReg = reg + gl * 8;
+ }
+ else
+ {
+ //Windowed register from the previous window
+ //Put it in the window before the one pointed to by cwp
+ newReg = numGlobals +
+ ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
+ }
+ }
+ else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
+ {
+ reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
+ if(reg < 8)
+ {
+ //Global register from the previous window
+ //Put it in the appropriate set of globals
+ newReg = reg + gl * 8;
+ }
+ else
+ {
+ //Windowed register from the next window
+ //Put it in the window after the one pointed to by cwp
+ newReg = numGlobals +
+ ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
+ }
+ }
+ else
+ panic("Tried to flatten invalid register index %d!\n", reg);
+ DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
+ return newReg;
+}
+
+void
+ISA::serialize(EventManager *em, std::ostream &os)
+{
+ miscRegFile.serialize(em, os);
+}
+
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
+{
+ miscRegFile.unserialize(em, cp, section);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_ISA_HH__
+#define __ARCH_SPARC_ISA_HH__
+
+#include "arch/sparc/miscregfile.hh"
+#include "arch/sparc/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace SparcISA
+{
+ class ISA
+ {
+ protected:
+ MiscRegFile miscRegFile;
+
+ public:
+
+ int instAsid()
+ {
+ return miscRegFile.getInstAsid();
+ }
+
+ int dataAsid()
+ {
+ return miscRegFile.getDataAsid();
+ }
+
+ void clear();
+
+ MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+ void setMiscRegNoEffect(int miscReg, const MiscReg val);
+ void setMiscReg(int miscReg, const MiscReg val,
+ ThreadContext *tc);
+
+ int flattenIntIndex(int reg);
+
+ int
+ flattenFloatIndex(int reg)
+ {
+ return reg;
+ }
+
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string §ion);
+
+ ISA()
+ {
+ clear();
+ }
+ };
+}
+
+#endif
{
floatRegFile.clear();
intRegFile.clear();
- miscRegFile.clear();
-}
-
-MiscReg RegFile::readMiscRegNoEffect(int miscReg)
-{
- return miscRegFile.readRegNoEffect(miscReg);
-}
-
-MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
-{
- return miscRegFile.readReg(miscReg, tc);
-}
-
-void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
-{
- miscRegFile.setRegNoEffect(miscReg, val);
-}
-
-void RegFile::setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc)
-{
- miscRegFile.setReg(miscReg, val, tc);
}
FloatReg RegFile::readFloatReg(int floatReg, int width)
intRegFile.setReg(intReg, val);
}
-int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
-{
- int gl = tc->readMiscRegNoEffect(MISCREG_GL);
- int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
- //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
- int newReg;
- //The total number of global registers
- int numGlobals = (MaxGL + 1) * 8;
- if(reg < 8)
- {
- //Global register
- //Put it in the appropriate set of globals
- newReg = reg + gl * 8;
- }
- else if(reg < NumIntArchRegs)
- {
- //Regular windowed register
- //Put it in the window pointed to by cwp
- newReg = numGlobals +
- ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
- }
- else if(reg < NumIntArchRegs + NumMicroIntRegs)
- {
- //Microcode register
- //Displace from the end of the regular registers
- newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
- }
- else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
- {
- reg -= (NumIntArchRegs + NumMicroIntRegs);
- if(reg < 8)
- {
- //Global register from the next window
- //Put it in the appropriate set of globals
- newReg = reg + gl * 8;
- }
- else
- {
- //Windowed register from the previous window
- //Put it in the window before the one pointed to by cwp
- newReg = numGlobals +
- ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
- }
- }
- else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
- {
- reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
- if(reg < 8)
- {
- //Global register from the previous window
- //Put it in the appropriate set of globals
- newReg = reg + gl * 8;
- }
- else
- {
- //Windowed register from the next window
- //Put it in the window after the one pointed to by cwp
- newReg = numGlobals +
- ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
- }
- }
- else
- panic("Tried to flatten invalid register index %d!\n", reg);
- DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
- return newReg;
- //return intRegFile.flattenIndex(reg);
-}
-
void
RegFile::serialize(EventManager *em, ostream &os)
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
- miscRegFile.serialize(em, os);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
- miscRegFile.unserialize(em, cp, section);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
protected:
IntRegFile intRegFile; // integer register file
FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
public:
void clear();
- MiscReg readMiscRegNoEffect(int miscReg);
-
- MiscReg readMiscReg(int miscReg, ThreadContext *tc);
-
- void setMiscRegNoEffect(int miscReg, const MiscReg &val);
-
- void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc);
-
- int instAsid()
- {
- return miscRegFile.getInstAsid();
- }
-
- int dataAsid()
- {
- return miscRegFile.getDataAsid();
- }
-
FloatReg readFloatReg(int floatReg, int width);
FloatReg readFloatReg(int floatReg);
public:
};
- int flattenIntIndex(ThreadContext * tc, int reg);
-
- static inline int
- flattenFloatIndex(ThreadContext * tc, int reg)
- {
- return reg;
- }
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
Source('insts/microregop.cc')
Source('insts/static_inst.cc')
Source('intregfile.cc')
+ Source('isa.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
Source('predecoder.cc')
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/isa.hh"
+#include "arch/x86/floatregs.hh"
+#include "cpu/thread_context.hh"
+
+namespace X86ISA
+{
+
+void
+ISA::clear()
+{
+ miscRegFile.clear();
+}
+
+MiscReg
+ISA::readMiscRegNoEffect(int miscReg)
+{
+ return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
+}
+
+MiscReg
+ISA::readMiscReg(int miscReg, ThreadContext *tc)
+{
+ return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
+}
+
+void
+ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
+{
+ miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
+}
+
+void
+ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
+{
+ miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
+}
+
+int
+ISA::flattenIntIndex(int reg)
+{
+ //If we need to fold over the index to match byte semantics, do that.
+ //Otherwise, just strip off any extra bits and pass it through.
+ if (reg & (1 << 6))
+ return (reg & (~(1 << 6) - 0x4));
+ else
+ return (reg & ~(1 << 6));
+}
+
+int
+ISA::flattenFloatIndex(int reg)
+{
+ if (reg >= NUM_FLOATREGS) {
+ int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
+ reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
+ }
+ return reg;
+}
+
+void
+ISA::serialize(EventManager *em, std::ostream &os)
+{
+ miscRegFile.serialize(os);
+}
+
+void
+ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
+{
+ miscRegFile.unserialize(cp, section);
+}
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_ISA_HH__
+#define __ARCH_X86_ISA_HH__
+
+#include "arch/x86/miscregfile.hh"
+#include "arch/x86/types.hh"
+
+class Checkpoint;
+class EventManager;
+
+namespace X86ISA
+{
+ class ISA
+ {
+ protected:
+ MiscRegFile miscRegFile;
+
+ public:
+ int instAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ int dataAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ void clear();
+
+ MiscReg readMiscRegNoEffect(int miscReg);
+ MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+
+ void setMiscRegNoEffect(int miscReg, const MiscReg val);
+ void setMiscReg(int miscReg, const MiscReg val,
+ ThreadContext *tc);
+
+ int flattenIntIndex(int reg);
+ int flattenFloatIndex(int reg);
+
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string §ion);
+ };
+}
+
+#endif
namespace X86ISA
{
- //These will have to be updated in the future.
- const int NumMiscArchRegs = NUM_MISCREGS;
- const int NumMiscRegs = NUM_MISCREGS;
-
class MiscRegFile
{
protected:
- MiscReg regVal[NumMiscRegs];
+ MiscReg regVal[NUM_MISCREGS];
void updateHandyM5Reg(Efer efer, CR0 cr0,
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
*/
#include "arch/x86/isa_traits.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/process.hh"
#include "arch/x86/segmentregs.hh"
#include "arch/x86/types.hh"
*/
#include "arch/x86/floatregs.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/regfile.hh"
#include "base/trace.hh"
#include "sim/serialize.hh"
{
floatRegFile.clear();
intRegFile.clear();
- miscRegFile.clear();
-}
-
-MiscReg RegFile::readMiscRegNoEffect(int miscReg)
-{
- return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
-}
-
-MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
-{
- return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
-}
-
-void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
-{
- miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
-}
-
-void RegFile::setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc)
-{
- miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
}
FloatReg RegFile::readFloatReg(int floatReg, int width)
intRegFile.setReg(intReg, val);
}
-int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
-{
- //If we need to fold over the index to match byte semantics, do that.
- //Otherwise, just strip off any extra bits and pass it through.
- if (reg & (1 << 6))
- return (reg & (~(1 << 6) - 0x4));
- else
- return (reg & ~(1 << 6));
-}
-
-int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
-{
- if (reg >= NUM_FLOATREGS) {
- int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP);
- reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
- }
- return reg;
-}
-
-void
-RegFile::serialize(EventManager *em, std::ostream &os)
-{
- intRegFile.serialize(os);
- floatRegFile.serialize(os);
- miscRegFile.serialize(os);
- SERIALIZE_SCALAR(rip);
- SERIALIZE_SCALAR(nextRip);
-}
-
void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
-{
- intRegFile.unserialize(cp, section);
- floatRegFile.unserialize(cp, section);
- miscRegFile.unserialize(cp, section);
- UNSERIALIZE_SCALAR(rip);
- UNSERIALIZE_SCALAR(nextRip);
-}
-
-void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
- //panic("copyMiscRegs not implemented for x86!\n");
warn("copyMiscRegs is naively implemented for x86\n");
- for (int i = 0; i < X86ISA::NumMiscRegs; ++i) {
+ for (int i = 0; i < NUM_MISCREGS; ++i) {
if ( ( i != MISCREG_CR1 &&
!(i > MISCREG_CR4 && i < MISCREG_CR8) &&
!(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
}
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}
-
}
-void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
+void
+X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
{
panic("copyRegs not implemented for x86!\n");
//copy int regs
dest->setPC(src->readPC());
dest->setNextPC(src->readNextPC());
}
+
+void
+RegFile::serialize(EventManager *em, std::ostream &os)
+{
+ intRegFile.serialize(os);
+ floatRegFile.serialize(os);
+}
+
+void
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
+{
+ intRegFile.unserialize(cp, section);
+ floatRegFile.unserialize(cp, section);
+}
#include "arch/x86/floatregfile.hh"
#include "arch/x86/intregfile.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/isa_traits.hh"
-#include "arch/x86/miscregfile.hh"
#include "arch/x86/types.hh"
#include "base/types.hh"
namespace X86ISA
{
+ const int NumMiscArchRegs = NUM_MISCREGS;
+ const int NumMiscRegs = NUM_MISCREGS;
+
class RegFile
{
protected:
protected:
IntRegFile intRegFile; // integer register file
FloatRegFile floatRegFile; // floating point register file
- MiscRegFile miscRegFile; // control register file
public:
void clear();
- MiscReg readMiscRegNoEffect(int miscReg);
-
- MiscReg readMiscReg(int miscReg, ThreadContext *tc);
-
- void setMiscRegNoEffect(int miscReg, const MiscReg &val);
-
- void setMiscReg(int miscReg, const MiscReg &val,
- ThreadContext * tc);
-
- int instAsid()
- {
- //XXX This doesn't make sense in x86
- return 0;
- }
-
- int dataAsid()
- {
- //XXX This doesn't make sense in x86
- return 0;
- }
-
FloatReg readFloatReg(int floatReg, int width);
FloatReg readFloatReg(int floatReg);
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string §ion);
-
- public:
};
- int flattenIntIndex(ThreadContext * tc, int reg);
-
- int flattenFloatIndex(ThreadContext * tc, int reg);
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
#include "config/full_system.hh"
#include "arch/x86/insts/microldstop.hh"
+#include "arch/x86/miscregs.hh"
#include "arch/x86/pagetable.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#ifndef __ARCH_X86_UTILITY_HH__
#define __ARCH_X86_UTILITY_HH__
+#include "arch/x86/miscregs.hh"
#include "arch/x86/types.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
coreType("default"),
_status(Idle),
tickEvent(this),
- miscRegFile(this),
timeBuffer(2 , 2),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
intRegFile[tid].clear();
floatRegFile[tid].clear();
- }
+ isa[tid].clear();
- // Update miscRegFile if necessary
- if (numThreads > 1) {
- miscRegFile.expandForMultithreading(numThreads, numVirtProcs);
+ isa[tid].expandForMultithreading(numThreads, numVirtProcs);
}
- miscRegFile.clear();
-
lastRunningCycle = curTick;
contextSwitch = false;
void
InOrderCPU::reset()
{
- miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this));
+ for (int i = 0; i < numThreads; i++) {
+ isa[i].reset(coreType, numThreads,
+ numVirtProcs, dynamic_cast<BaseCPU*>(this));
+ }
}
Port*
MiscReg
InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
- return miscRegFile.readRegNoEffect(misc_reg, tid);
+ return isa[tid].readMiscRegNoEffect(misc_reg);
}
MiscReg
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
{
- return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
+ return isa[tid].readMiscReg(misc_reg, tcBase(tid));
}
void
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
{
- miscRegFile.setRegNoEffect(misc_reg, val, tid);
+ isa[tid].setMiscRegNoEffect(misc_reg, val);
}
void
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
{
- miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
+ isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
}
#include <vector>
#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "base/types.hh"
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscReg MiscReg;
typedef TheISA::RegFile RegFile;
+ typedef TheISA::MiscReg MiscReg;
//DynInstPtr TypeDefs
typedef ThePipeline::DynInstPtr DynInstPtr;
/** The Register File for the CPU */
TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
- TheISA::MiscRegFile miscRegFile;
+
+ /** ISA state */
+ TheISA::ISA isa[ThePipeline::MaxThreads];
/** Dependency Tracker for Integer & Floating Point Regs */
RegDepMap archRegDepMap[ThePipeline::MaxThreads];
* write might have as defined by the architecture. */
virtual void setMiscReg(int misc_reg, const MiscReg &val);
+ virtual int flattenIntIndex(int reg)
+ { return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
+
+ virtual int flattenFloatIndex(int reg)
+ { return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
+
virtual void activateContext(int delay)
{ cpu->activateContext(thread->readTid(), delay); }
TheISA::MiscReg
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
- return this->regFile.readMiscRegNoEffect(misc_reg, tid);
+ return this->isa[tid].readMiscRegNoEffect(misc_reg);
}
template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
- return this->regFile.readMiscReg(misc_reg, tid);
+ return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
}
template <class Impl>
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
const TheISA::MiscReg &val, ThreadID tid)
{
- this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
+ this->isa[tid].setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
FullO3CPU<Impl>::setMiscReg(int misc_reg,
const TheISA::MiscReg &val, ThreadID tid)
{
- this->regFile.setMiscReg(misc_reg, val, tid);
+ this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
}
template <class Impl>
/** Get instruction asid. */
int getInstAsid(ThreadID tid)
- { return regFile.miscRegs[tid].getInstAsid(); }
+ { return isa[tid].instAsid(); }
/** Get data asid. */
int getDataAsid(ThreadID tid)
- { return regFile.miscRegs[tid].getDataAsid(); }
+ { return isa[tid].dataAsid(); }
#else
/** Get instruction asid. */
int getInstAsid(ThreadID tid)
/** Integer Register Scoreboard */
Scoreboard scoreboard;
+ TheISA::ISA isa[Impl::MaxThreads];
+
public:
/** Enum to give each stage a specific index, so when calling
* activateStage() or deactivateStage(), they can specify which stage
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscRegFile MiscRegFile;
- typedef TheISA::MiscReg MiscReg;
typedef union {
FloatReg d;
floatRegFile[reg_idx].q = val;
}
- MiscReg
- readMiscRegNoEffect(int misc_reg, ThreadID tid)
- {
- return miscRegs[tid].readRegNoEffect(misc_reg);
- }
-
- MiscReg
- readMiscReg(int misc_reg, ThreadID tid)
- {
- return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid));
- }
-
- void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
- {
- miscRegs[tid].setRegNoEffect(misc_reg, val);
- }
-
- void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
- {
- miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid));
- }
-
public:
/** (signed) integer register file. */
IntReg *intRegFile;
/** Floating point register file. */
PhysFloatReg *floatRegFile;
- /** Miscellaneous register file. */
- MiscRegFile miscRegs[Impl::MaxThreads];
-
#if FULL_SYSTEM
private:
int intrflag; // interrupt flag
intRegFile = new IntReg[numPhysicalIntRegs];
floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
- for (int i = 0; i < Impl::MaxThreads; ++i) {
- miscRegs[i].clear();
- }
-
memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
}
RegIndex src_reg = inst->srcRegIdx(src_idx);
RegIndex flat_src_reg = src_reg;
if (src_reg < TheISA::FP_Base_DepTag) {
- flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
+ flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
} else if (src_reg < TheISA::Ctrl_Base_DepTag) {
src_reg = src_reg - TheISA::FP_Base_DepTag;
- flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg);
+ flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
flat_src_reg += TheISA::NumIntRegs;
} else {
flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
RegIndex flat_dest_reg = dest_reg;
if (dest_reg < TheISA::FP_Base_DepTag) {
// Integer registers are flattened.
- flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
+ flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
} else {
// Floating point and Miscellaneous registers need their indexes
* write might have as defined by the architecture. */
virtual void setMiscReg(int misc_reg, const MiscReg &val);
+ virtual int flattenIntIndex(int reg);
+ virtual int flattenFloatIndex(int reg);
+
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.
virtual unsigned readStCondFailures()
uint64_t
O3ThreadContext<Impl>::readIntReg(int reg_idx)
{
- reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
return cpu->readArchIntReg(reg_idx, thread->threadId());
}
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
switch(width) {
case 32:
return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
}
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
{
DPRINTF(Fault, "Reading floatint register through the TC!\n");
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
}
TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
}
void
O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
{
- reg_idx = TheISA::flattenIntIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
cpu->setArchIntReg(reg_idx, val, thread->threadId());
// Squash if we're not already in a state update mode.
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
switch(width) {
case 32:
cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
if (!thread->trapPending && !thread->inSyscall) {
int width)
{
DPRINTF(Fault, "Setting floatint register through the TC!\n");
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
// Squash if we're not already in a state update mode.
void
O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
+ reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
// Squash if we're not already in a state update mode.
}
}
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenIntIndex(int reg)
+{
+ return cpu->isa[thread->threadId()].flattenIntIndex(reg);
+}
+
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenFloatIndex(int reg)
+{
+ return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
+}
+
template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
#ifndef __CPU_SIMPLE_THREAD_HH__
#define __CPU_SIMPLE_THREAD_HH__
+#include "arch/isa.hh"
#include "arch/isa_traits.hh"
#include "arch/regfile.hh"
#include "arch/tlb.hh"
protected:
typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
- typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
protected:
RegFile regs; // correct-path register context
+ TheISA::ISA isa; // one "instance" of the current ISA.
public:
// pointer to CPU associated with this SimpleThread
}
#if FULL_SYSTEM
- int getInstAsid() { return regs.instAsid(); }
- int getDataAsid() { return regs.dataAsid(); }
+ int getInstAsid() { return isa.instAsid(); }
+ int getDataAsid() { return isa.dataAsid(); }
void dumpFuncProfile();
//
uint64_t readIntReg(int reg_idx)
{
- int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenIntIndex(reg_idx);
return regs.readIntReg(flatIndex);
}
FloatReg readFloatReg(int reg_idx, int width)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
return regs.readFloatReg(flatIndex, width);
}
FloatReg readFloatReg(int reg_idx)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
return regs.readFloatReg(flatIndex);
}
FloatRegBits readFloatRegBits(int reg_idx, int width)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
return regs.readFloatRegBits(flatIndex, width);
}
FloatRegBits readFloatRegBits(int reg_idx)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
return regs.readFloatRegBits(flatIndex);
}
void setIntReg(int reg_idx, uint64_t val)
{
- int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenIntIndex(reg_idx);
regs.setIntReg(flatIndex, val);
}
void setFloatReg(int reg_idx, FloatReg val, int width)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
regs.setFloatReg(flatIndex, val, width);
}
void setFloatReg(int reg_idx, FloatReg val)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
regs.setFloatReg(flatIndex, val);
}
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
regs.setFloatRegBits(flatIndex, val, width);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
+ int flatIndex = isa.flattenFloatIndex(reg_idx);
regs.setFloatRegBits(flatIndex, val);
}
MiscReg
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
{
- return regs.readMiscRegNoEffect(misc_reg);
+ return isa.readMiscRegNoEffect(misc_reg);
}
MiscReg
readMiscReg(int misc_reg, ThreadID tid = 0)
{
- return regs.readMiscReg(misc_reg, tc);
+ return isa.readMiscReg(misc_reg, tc);
}
void
setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
- return regs.setMiscRegNoEffect(misc_reg, val);
+ return isa.setMiscRegNoEffect(misc_reg, val);
}
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
- return regs.setMiscReg(misc_reg, val, tc);
+ return isa.setMiscReg(misc_reg, val, tc);
+ }
+
+ int
+ flattenIntIndex(int reg)
+ {
+ return isa.flattenIntIndex(reg);
+ }
+
+ int
+ flattenFloatIndex(int reg)
+ {
+ return isa.flattenFloatIndex(reg);
}
unsigned readStCondFailures() { return storeCondFailures; }
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
public:
virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
+ virtual int flattenIntIndex(int reg) = 0;
+ virtual int flattenFloatIndex(int reg) = 0;
+
virtual uint64_t
readRegOtherThread(int misc_reg, ThreadID tid)
{
void setMiscReg(int misc_reg, const MiscReg &val)
{ return actualTC->setMiscReg(misc_reg, val); }
+ int flattenIntIndex(int reg)
+ { return actualTC->flattenIntIndex(reg); }
+
+ int flattenFloatIndex(int reg)
+ { return actualTC->flattenFloatIndex(reg); }
+
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
#include <string.h> // for memset()
#include <unistd.h>
+#include "arch/alpha/miscregfile.hh"
#include "cpu/base.hh"
#include "sim/core.hh"
#include "sim/syscall_emul.hh"
projects / gem5.git / commitdiff