Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v

diff --git a/techlibs/simlib.v b/techlibs/simlib.v
index 8675a4d0fceeafc1d31506f427034487095af5df..ff988cbe560e545658656da5c35fe532307f00dc 100644 (file)
--- a/techlibs/simlib.v
+++ b/techlibs/simlib.v
@@ -799,8 +799,8 @@ parameter MEMID = "";
 parameter ABITS = 8;
 parameter WIDTH = 8;
 
-parameter RD_CLK_ENABLE = 0;
-parameter RD_CLK_POLARITY = 0;
+parameter CLK_ENABLE = 0;
+parameter CLK_POLARITY = 0;
 
 input CLK;
 input [ABITS-1:0] ADDR;
@@ -821,8 +821,8 @@ parameter MEMID = "";
 parameter ABITS = 8;
 parameter WIDTH = 8;
 
-parameter RD_CLK_ENABLE = 0;
-parameter RD_CLK_POLARITY = 0;
+parameter CLK_ENABLE = 0;
+parameter CLK_POLARITY = 0;
 
 input CLK, EN;
 input [ABITS-1:0] ADDR;