arch-arm: only change the pc address when GDB registers are set

The entire pcState was being reset, which made the simulation incorrectly
switch to aarch32 from aarch64.

Change-Id: I9ba7dd0ed95bc6120d94393bba272e0cb8c081c5
Reviewed-on: https://gem5-review.googlesource.com/c/14496
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index a395cd91300ac8c7dd5f46fe27ab5972d2a93a3b..38207d4942cbe1abe7bd51ee3d3593b444a648d0 100644 (file)
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -218,7 +218,9 @@ RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const
 
     for (int i = 0; i < 31; ++i)
         context->setIntReg(INTREG_X0 + i, r.x[i]);
-    context->pcState(r.pc);
+    auto pc_state = context->pcState();
+    pc_state.set(r.pc);
+    context->pcState(pc_state);
     context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
     // Update the stack pointer. This should be done after
     // updating CPSR/PSTATE since that might affect how SPX gets
@@ -282,7 +284,9 @@ RemoteGDB::AArch32GdbRegCache::setRegs(ThreadContext *context) const
     context->setIntReg(INTREG_R12, r.gpr[12]);
     context->setIntReg(INTREG_SP, r.gpr[13]);
     context->setIntReg(INTREG_LR, r.gpr[14]);
-    context->pcState(r.gpr[15]);
+    auto pc_state = context->pcState();
+    pc_state.set(r.gpr[15]);
+    context->pcState(pc_state);
 
     // One day somebody will implement transfer of FPRs correctly.