(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 45e54f224678d273cf3b413dec99dceb3f21d6cb..255725dbadb2708088b0500fb47d9bd71a840d3a 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -58,11 +58,14 @@ Other modes are still applicable and include:
 for analysing a Vector of Condition Register Fields
 and reducing it to one
 single Condition Register Field.
+* **Pack/Unpack Mode**.
+  Like VSX `vpack` and `vunpack` the source and destination
+  elements are reordered.
 
-Predicate-result unfortunately does not make any sense because
+Predicate-result does not make any sense because
 when Rc=1 a co-result is created (a CR Field). Testing the co-result
 allows the decision to be made to store or not store the main
-result, and unfortunately for CR Ops the CR Field result *is*
+result, and for CR Ops the CR Field result *is*
 the main result.
 
 # Format
@@ -71,11 +74,11 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 
 | 6 | 7 | 19-20 |  21 | 22   23 |  description     |
 | - | - | ----- | --- |---------|----------------- |
-|sz |SNZ| 0 RG  |   0 | dz  0   | normal mode                      |
-|sz |SNZ| 0 RG  |   0 | dz  1   | Pack/Unpack mode                 |
+|sz |SNZ| 0 RG  |   0 | dz  /   | normal mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
 |zz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
-|sz |SNZ| 0 RG  |   1 | SVM /   | subvector reduce mode, SUBVL>1   |
+|sz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
+|sz |SNZ| 0 RG  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
 |sz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |