Merge branch 'read_aiger' into xaig

diff --cc Makefile
Simple merge

diff --cc frontends/aiger/aigerparse.cc
index 6fa77282ee2d59b219a6cf476b9bbafe0b14e0fe,cf7950c85557a300f2d4f88fe2d4d3d848e19be7..45cacadb65dbb89e6cd29de4e272db9289654364
--- 1/frontends/aiger/aigerparse.cc
--- 2/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@@ -22,12 -22,13 +22,15 @@@
  // Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
  // http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
  
 -#ifndef _WIN32
 +#ifdef _WIN32
+ #include <libgen.h>
 +#include <stdlib.h>
  #endif
+ #include <array>
+ 
  #include "kernel/yosys.h"
  #include "kernel/sigtools.h"
 +#include "kernel/consteval.h"
  #include "aigerparse.h"
  
  YOSYS_NAMESPACE_BEGIN
@@@ -581,9 -238,9 +584,9 @@@ void AigerReader::parse_aiger_ascii(
          RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
          RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
          RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 -        module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
 +        module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
      }
-     std::getline(f, line);
+     std::getline(f, line); // Ignore up to start of next line
  }
  
  static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
@@@ -775,11 -398,11 +778,13 @@@ struct AigerFrontend : public Frontend 
  
          if (module_name.empty()) {
  #ifdef _WIN32
 -            module_name = "top"; // FIXME: basename equivalent on Win32?
 +            char fname[_MAX_FNAME];
 +            _splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */)
 +            module_name = fname;
  #else
-             module_name = RTLIL::escape_id(basename(filename.c_str()));
+             char* bn = strdup(filename.c_str());
+             module_name = RTLIL::escape_id(bn);
+             free(bn);
  #endif
          }