mention SVP64 in ls005

diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn
index a66b4234e42f5872f0245e9f0f98a90c558893bb..22888b94c0c1b99ea8301661b60565366e434763 100644 (file)
--- a/openpower/sv/rfc/ls005.mdwn
+++ b/openpower/sv/rfc/ls005.mdwn
@@ -85,6 +85,11 @@ this with the more "normal" approach of creating heavily-focussed
 specialist "AI" Engines incapable of Turing-completeness and the benefits
 are clear.
 
+Note: SVP64 **requires** this change as a 100% critical dependency.
+SIMD back-end ALUs process Vectors of "Elements" at 8, 16 and 32-bit (and
+64-bit), read from, processed, and returned to, the standard **Scalar**
+Register Files, with byte-level write-enable lines.
+
 **Changes**
 
 For all pseudocode right across the board in all Scalar operations, replace