re PR rtl-optimization/89676 (Redundant moves for long long shift on 32bit x86)

2019-03-25  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/89676
	* lra-constraints.c (curr_insn_transform): Do match reload for
	early clobbers when the match was successful only for different
	registers.

From-SVN: r269924

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 62c23d45a5a1bf8ac1b136fbbfe10812181052da..2075480ca2beefc0ae7260ed2cf598c7beaf6e78 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-03-25  Vladimir Makarov  <vmakarov@redhat.com>
+
+       PR rtl-optimization/89676
+       * lra-constraints.c (curr_insn_transform): Do match reload for
+       early clobbers when the match was successful only for different
+       registers.
+
 2019-03-25  Martin Sebor  <msebor@redhat.com>
 
        * doc/extend.texi (Common Type Attributes): Document vector_size.

diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index 78932cc1538d8151372ca2d25e40ef1aad5fff88..cf33da8013e4679b0912ad47052956c35839494b 100644 (file)
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -4259,15 +4259,27 @@ curr_insn_transform (bool check_only_p)
          else if (goal_alt_matched[i][0] != -1
                   && curr_static_id->operand[i].type == OP_OUT
                   && (curr_static_id->operand_alternative
-                      [goal_alt_number * n_operands + i].earlyclobber))
+                      [goal_alt_number * n_operands + i].earlyclobber)
+                  && REG_P (op))
            {
-             /* Generate reloads for output and matched inputs.  This
-                is the easiest way to avoid creation of non-existing
-                conflicts in lra-lives.c.  */
-             match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
-                           &after, TRUE);
-             outputs[n_outputs++] = i;
-             outputs[n_outputs] = -1;
+             for (j = 0; goal_alt_matched[i][j] != -1; j++)
+               {
+                 rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]];
+                 
+                 if (REG_P (op2) && REGNO (op) != REGNO (op2))
+                   break;
+               }
+             if (goal_alt_matched[i][j] != -1)
+               {
+                 /* Generate reloads for different output and matched
+                    input registers.  This is the easiest way to avoid
+                    creation of non-existing register conflicts in
+                    lra-lives.c.  */
+                 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
+                               &after, TRUE);
+                 outputs[n_outputs++] = i;
+                 outputs[n_outputs] = -1;
+               }
              continue;
            }
          else