[libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA

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+Date: Thu, 21 May 2020 13:02:18 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Formal Verification
+X-Bugzilla-Version: unspecified
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-195-13-H7nur4ZwEs@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 195] Formal correctness framework is needed
+ for Power ISA
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