Started implementing microcode.

--HG--
extra : convert_revision : 51df0454085e13df023efd8a0c0a12f9756c4690

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0bbe9228226798e704b1464e041c5eb87e8cb401..1d5c0a6f5f170f1af9dac9f5b44f9ed14bcb8a35 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -396,7 +396,18 @@ BaseSimpleCPU::preExecute()
 
     // decode the instruction
     inst = gtoh(inst);
-    curStaticInst = StaticInst::decode(makeExtMI(inst, thread->getTC()));
+    //If we're not in the middle of a macro instruction
+    if (!curMacroStaticInst) {
+        StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
+        if (instPtr->isMacroOp()) {
+            curMacroStaticInst = instPtr;
+            curStaticInst = curMacroStaticInst->fetchMicroOp(0);
+        }
+    } else {
+        //Read the next micro op from the macro op
+        curStaticInst = curMacroStaticInst->fetchMicroOp(thread->readMicroPc());
+    }
+
 
     traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
                                      thread->readPC());
@@ -446,18 +457,35 @@ BaseSimpleCPU::advancePC(Fault fault)
 {
     if (fault != NoFault) {
         fault->invoke(tc);
-    }
-    else {
-        // go to the next instruction
-        thread->setPC(thread->readNextPC());
+    } else {
+        //If we're at the last micro op for this instruction
+        if (curStaticInst->isLastMicroOp()) {
+            //We should be working with a macro op
+            assert(curMacroStaticInst);
+            //Close out this macro op, and clean up the
+            //microcode state
+            curMacroStaticInst = nullStaticInst;
+            thread->setMicroPC(0);
+            thread->setNextMicroPC(0);
+        }
+        //If we're still in a macro op
+        if (curMacroStaticInst) {
+            //Advance the micro pc
+            thread->setMicroPC(thread->getNextMicroPC());
+            //Advance the "next" micro pc. Note that there are no delay
+            //slots, and micro ops are "word" addressed.
+            thread->setNextMicroPC(thread->getNextMicroPC() + 1);
+        } else {
+            // go to the next instruction
+            thread->setPC(thread->readNextPC());
 #if ISA_HAS_DELAY_SLOT
-        thread->setNextPC(thread->readNextNPC());
-        thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
-        assert(thread->readNextPC() != thread->readNextNPC());
+            thread->setNextPC(thread->readNextNPC());
+            thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
+            assert(thread->readNextPC() != thread->readNextNPC());
 #else
-        thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
+            thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 #endif
-
+        }
     }
 
 #if FULL_SYSTEM

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 57cfa3c2cddf69812a8b97c7a9001f1e1e3ec85c..af6b6f8352e7a08bbe60cc4d03b8ef947c36cfa4 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -128,6 +128,7 @@ class BaseSimpleCPU : public BaseCPU
     TheISA::IntReg dataReg;
 
     StaticInstPtr curStaticInst;
+    StaticInstPtr curMacroStaticInst;
 
     void checkForInterrupts();
     Fault setupFetchRequest(Request *req);

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 6fa6500bda6554c25ec3cf20c5e2d08dec29d772..fe22e6c43d25c3a2a4a61d556f9dc4de30f45a8b 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -377,6 +377,16 @@ class SimpleThread : public ThreadState
         regs.setPC(val);
     }
 
+    uint64_t readMicroPC()
+    {
+        return microPC;
+    }
+
+    void setMicroPC(uint64_t val)
+    {
+        microPC = val;
+    }
+
     uint64_t readNextPC()
     {
         return regs.readNextPC();
@@ -387,6 +397,16 @@ class SimpleThread : public ThreadState
         regs.setNextPC(val);
     }
 
+    uint64_t readNextMicroPC()
+    {
+        return nextMicroPC;
+    }
+
+    void setNextMicroPC(uint64_t val)
+    {
+        nextMicroPC = val;
+    }
+
     uint64_t readNextNPC()
     {
         return regs.readNextNPC();

diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 14e033b7fbb02620807eb646397e7d84c35b2777..60353760c5912a6923d86c4549b0d623a44d31f5 100644 (file)
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -200,6 +200,16 @@ struct ThreadState {
      */
     TheISA::MachInst inst;
 
+    /** The current microcode pc for the currently executing macro
+     * operation.
+     */
+    MicroPC microPC;
+
+    /** The next microcode pc for the currently executing macro
+     * operation.
+     */
+    MicroPC nextMicroPC;
+
   public:
     /**
      * Temporary storage to pass the source address from copy_load to