+2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/arm/arm.h (TARGET_USE_MOVT): Check MOVT/MOVW availability
+ with TARGET_HAVE_MOVT.
+ (TARGET_HAVE_MOVT): Define.
+ * config/arm/arm.c (const_ok_for_op): Check MOVT/MOVW
+ availability with TARGET_HAVE_MOVT.
+ * config/arm/arm.md (arm_movt): Use TARGET_HAVE_MOVT to check MOVT
+ availability.
+ (addsi splitter): Use TARGET_THUMB && TARGET_HAVE_MOVT rather than
+ TARGET_THUMB2.
+ (symbol_refs movsi splitter): Remove TARGET_32BIT check.
+ (arm_movtas_ze): Use TARGET_HAVE_MOVT to check MOVT availability.
+ * config/arm/constraints.md (define_constraint "j"): Use
+ TARGET_HAVE_MOVT to check MOVT availability.
+
2016-07-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm-protos.h: Reindent FL_FOR_* macro definitions.
{
case SET:
/* See if we can use movw. */
- if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
+ if (TARGET_HAVE_MOVT && (i & 0xffff0000) == 0)
return 1;
else
/* Otherwise, try mvn. */
/* Should MOVW/MOVT be used in preference to a constant pool. */
#define TARGET_USE_MOVT \
- (arm_arch_thumb2 \
+ (TARGET_HAVE_MOVT \
&& (arm_disable_literal_pool \
|| (!optimize_size && !current_tune->prefer_constant_pool)))
/* Nonzero if this chip supports load-acquire and store-release. */
#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
+/* Nonzero if this chip provides the MOVW and MOVW instructions. */
+#define TARGET_HAVE_MOVT (arm_arch_thumb2)
+
/* Nonzero if integer division instructions supported. */
#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
|| (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "general_operand" "i")))]
- "arm_arch_thumb2 && arm_valid_symbolic_address_p (operands[2])"
+ "TARGET_HAVE_MOVT && arm_valid_symbolic_address_p (operands[2])"
"movt%?\t%0, #:upper16:%c2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
[(set (match_operand:SI 0 "arm_general_register_operand" "")
(const:SI (plus:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "const_int_operand" ""))))]
- "TARGET_THUMB2
+ "TARGET_THUMB
+ && TARGET_HAVE_MOVT
&& arm_disable_literal_pool
&& reload_completed
&& GET_CODE (operands[1]) == SYMBOL_REF"
(define_split
[(set (match_operand:SI 0 "arm_general_register_operand" "")
(match_operand:SI 1 "general_operand" ""))]
- "TARGET_32BIT
- && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
+ "TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
&& !flag_pic && !target_word_relocations
&& !arm_tls_referenced_p (operands[1])"
[(clobber (const_int 0))]
(const_int 16)
(const_int 16))
(match_operand:SI 1 "const_int_operand" ""))]
- "arm_arch_thumb2"
+ "TARGET_HAVE_MOVT"
"movt%?\t%0, %L1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(define_constraint "j"
"A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
- (and (match_test "TARGET_32BIT && arm_arch_thumb2")
+ (and (match_test "TARGET_HAVE_MOVT")
(ior (and (match_code "high")
(match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
(and (match_code "const_int")