from migen.bank.description import *
from migen.fhdl.simplify import *
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
from misoclib.ethmac.preamble import PreambleInserter, PreambleChecker
from migen.actorlib.crc import CRC32Inserter, CRC32Checker
from misoclib.ethmac.last_be import TXLastBE, RXLastBE
self.submodules.tx_pipeline = Pipeline(*tx_pipeline)
if interface == "wishbone":
- nrxslots=2
- ntxslots=2
+ nrxslots = 2
+ ntxslots = 2
self.bus = wishbone.Interface()
# Interface
wb_rx_sram_ifs = [wishbone.SRAM(self.sram_writer.mems[n], read_only=True)
for n in range(nrxslots)]
+ # TODO: FullMemoryWE should move to Mibuild
wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram_reader.mems[n], read_only=False))
for n in range(ntxslots)]
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
--- /dev/null
+from migen.fhdl.std import *
+from migen.flow.actor import EndpointDescription
+
+eth_mtu = 1532
+eth_preamble = 0xD555555555555555
+buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
+
+def eth_description(dw):
+ parameters = {
+ "packetized": True
+ }
+ layout = [
+ ("d", dw),
+ ("last_be", dw//8),
+ ("error", dw//8)
+ ]
+ return EndpointDescription(layout, parameters)
from migen.genlib.record import *
from migen.flow.actor import Sink, Source
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
class TXLastBE(Module):
def __init__(self, d_w):
self.sink = sink = Sink(eth_description(d_w))
self.source = source = Source(eth_description(d_w))
+
###
+
ongoing = Signal()
self.sync += \
If(self.sink.stb & self.sink.ack,
def __init__(self, d_w):
self.sink = sink = Sink(eth_description(d_w))
self.source = source = Source(eth_description(d_w))
+
###
+
+ # TODO/FIXME
fake = Signal() # to use RenameClockDomain
self.sync += fake.eq(1)
self.comb += [
--- /dev/null
+from migen.fhdl.std import *
+from migen.flow.actor import Sink, Source
+from migen.bank.description import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoclib.ethmac.common import *
+
+class GMIIPHYTX(Module):
+ def __init__(self, pads):
+ self.sink = sink = Sink(eth_description(8))
+
+ ###
+
+ self.sync += [
+ pads.tx_er.eq(0),
+ pads.tx_en.eq(sink.stb),
+ pads.tx_data.eq(sink.d)
+ ]
+ self.comb += sink.ack.eq(1)
+
+class GMIIPHYRX(Module):
+ def __init__(self, pads):
+ self.source = source = Source(eth_description(8))
+
+ ###
+
+ dv_d = Signal()
+ self.sync += dv_d.eq(pads.dv)
+
+ sop = Signal()
+ eop = Signal()
+ self.comb += [
+ sop.eq(pads.dv & ~dv_d),
+ eop.eq(~pads.dv & dv_d)
+ ]
+ self.sync += [
+ source.stb.eq(pads.dv),
+ source.sop.eq(sop),
+ source.d.eq(pads.rx_data)
+ ]
+ self.comb += source.eop.eq(eop)
+
+# CRG is the only Xilinx specific module.
+# TODO: use generic code or add support for others vendors
+class GMIIPHYCRG(Module, AutoCSR):
+ def __init__(self, clock_pads, pads):
+ self._reset = CSRStorage()
+
+ ###
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+ self.specials += [
+ Instance("ODDR",
+ p_DDR_CLK_EDGE="SAME_EDGE",
+ i_C=ClockSignal("eth_tx"), i_CE=1, i_S=0, i_R=0,
+ i_D1=1, i_D2=0, o_Q=clock_pads.gtx,
+ ),
+ Instance("BUFG", i_I=clock_pads.rx, o_O=self.cd_eth_rx.clk),
+ ]
+ self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
+
+ reset = self._reset.storage
+ self.comb += pads.rst_n.eq(~reset)
+ self.specials += [
+ AsyncResetSynchronizer(self.cd_eth_tx, reset),
+ AsyncResetSynchronizer(self.cd_eth_rx, reset),
+ ]
+
+class GMIIPHY(Module, AutoCSR):
+ def __init__(self, clock_pads, pads):
+ self.dw = 8
+ self.submodules.crg = GMIIPHYCRG(clock_pads, pads)
+ self.submodules.tx = RenameClockDomains(GMIIPHYTX(pads), "eth_tx")
+ self.submodules.rx = RenameClockDomains(GMIIPHYRX(pads), "eth_rx")
+ self.sink, self.source = self.tx.sink, self.rx.source
--- /dev/null
+from migen.fhdl.std import *
+from migen.flow.actor import Sink, Source
+from migen.bank.description import *
+from migen.genlib.record import *
+
+from misoclib.ethmac.common import *
+
+class LoopbackPHYCRG(Module, AutoCSR):
+ def __init__(self):
+ self._reset = CSRStorage()
+
+ ###
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+ self.comb += [
+ self.cd_eth_rx.clk.eq(ClockSignal()),
+ self.cd_eth_tx.clk.eq(ClockSignal())
+ ]
+
+ reset = self._reset.storage
+ self.comb += [
+ self.cd_eth_rx.rst.eq(reset),
+ self.cd_eth_tx.rst.eq(reset)
+ ]
+
+class LoopbackPHY(Module, AutoCSR):
+ def __init__(self):
+ self.dw = 8
+ self.submodules.crg = LoopbackPHYCRG()
+ self.sink = sink = Sink(eth_description(8))
+ self.source = source = Source(eth_description(8))
+ self.comb += Record.connect(self.sink, self.source)
--- /dev/null
+from migen.fhdl.std import *
+from migen.genlib.fsm import FSM, NextState
+from migen.flow.actor import Sink, Source
+from migen.bank.description import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoclib.ethmac.common import *
+
+class MIIPHYTX(Module):
+ def __init__(self, pads):
+ self.sink = sink = Sink(eth_description(8))
+
+ ###
+
+ tx_en_r = Signal()
+ tx_data_r = Signal(4)
+ self.sync += [
+ pads.tx_er.eq(0),
+ pads.tx_en.eq(tx_en_r),
+ pads.tx_data.eq(tx_data_r),
+ ]
+
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += fsm
+ fsm.act("IDLE",
+ sink.ack.eq(1),
+ If(sink.stb & sink.sop,
+ sink.ack.eq(0),
+ NextState("SEND_LO")
+ )
+ )
+ fsm.act("SEND_LO",
+ tx_data_r.eq(sink.d[0:4]),
+ tx_en_r.eq(1),
+ NextState("SEND_HI")
+ )
+ fsm.act("SEND_HI",
+ tx_data_r.eq(sink.d[4:8]),
+ tx_en_r.eq(1),
+ sink.ack.eq(1),
+ If(sink.stb & sink.eop,
+ NextState("IDLE")
+ ).Else(
+ NextState("SEND_LO")
+ )
+ )
+
+class MIIPHYRX(Module):
+ def __init__(self, pads):
+ self.source = source = Source(eth_description(8))
+
+ ###
+
+ sop = source.sop
+ set_sop = Signal()
+ clr_sop = Signal()
+ self.sync += \
+ If(clr_sop,
+ sop.eq(0)
+ ).Elif(set_sop,
+ sop.eq(1)
+ )
+
+ lo = Signal(4)
+ hi = Signal(4)
+ load_nibble = Signal(2)
+ self.sync += \
+ If(load_nibble[0],
+ lo.eq(pads.rx_data)
+ ).Elif(load_nibble[1],
+ hi.eq(pads.rx_data)
+ )
+ self.comb += [
+ source.d.eq(Cat(lo, hi))
+ ]
+
+ fsm = FSM(reset_state="IDLE")
+ self.submodules += fsm
+ fsm.act("IDLE",
+ set_sop.eq(1),
+ If(pads.dv,
+ load_nibble.eq(0b01),
+ NextState("LOAD_HI")
+ )
+ )
+ fsm.act("LOAD_LO",
+ source.stb.eq(1),
+ If(pads.dv,
+ clr_sop.eq(1),
+ load_nibble.eq(0b01),
+ NextState("LOAD_HI")
+ ).Else(
+ source.eop.eq(1),
+ NextState("IDLE")
+ )
+ )
+ fsm.act("LOAD_HI",
+ load_nibble.eq(0b10),
+ NextState("LOAD_LO")
+ )
+
+class MIIPHYCRG(Module, AutoCSR):
+ def __init__(self, clock_pads, pads):
+ self._reset = CSRStorage()
+
+ ###
+
+ self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
+
+ self.clock_domains.cd_eth_rx = ClockDomain()
+ self.clock_domains.cd_eth_tx = ClockDomain()
+ self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
+ self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
+
+ reset = self._reset.storage
+ self.comb += pads.rst_n.eq(~reset)
+ self.specials += [
+ AsyncResetSynchronizer(self.cd_eth_tx, reset),
+ AsyncResetSynchronizer(self.cd_eth_rx, reset),
+ ]
+
+class MIIPHY(Module, AutoCSR):
+ def __init__(self, clock_pads, pads):
+ self.dw = 8
+ self.submodules.crg = MIIPHYCRG(clock_pads, pads)
+ self.submodules.tx = RenameClockDomains(MIIPHYTX(pads), "eth_tx")
+ self.submodules.rx = RenameClockDomains(MIIPHYRX(pads), "eth_rx")
+ self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from migen.fhdl.std import *
-from migen.flow.actor import Sink, Source
-from migen.bank.description import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoclib.ethmac.std import *
-
-class GMIIPHYTX(Module):
- def __init__(self, pads):
- self.sink = sink = Sink(eth_description(8))
- ###
- self.sync += [
- pads.tx_er.eq(0),
- pads.tx_en.eq(sink.stb),
- pads.tx_data.eq(sink.d)
- ]
- self.comb += sink.ack.eq(1)
-
-class GMIIPHYRX(Module):
- def __init__(self, pads):
- self.source = source = Source(eth_description(8))
- ###
- dv_d = Signal()
- self.sync += dv_d.eq(pads.dv)
-
- sop = Signal()
- eop = Signal()
- self.comb += [
- sop.eq(pads.dv & ~dv_d),
- eop.eq(~pads.dv & dv_d)
- ]
- self.sync += [
- source.stb.eq(pads.dv),
- source.sop.eq(sop),
- source.d.eq(pads.rx_data)
- ]
- self.comb += source.eop.eq(eop)
-
-# CRG is the only Xilinx specific module.
-# Todo: use generic code or add support for others vendors
-class GMIIPHYCRG(Module, AutoCSR):
- def __init__(self, clock_pads, pads):
- self._reset = CSRStorage()
- ###
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.specials += [
- Instance("ODDR",
- p_DDR_CLK_EDGE="SAME_EDGE",
- i_C=ClockSignal("eth_tx"), i_CE=1, i_S=0, i_R=0,
- i_D1=1, i_D2=0, o_Q=clock_pads.gtx,
- ),
- Instance("BUFG", i_I=clock_pads.rx, o_O=self.cd_eth_rx.clk),
- ]
- self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
-
- reset = self._reset.storage
- self.comb += pads.rst_n.eq(~reset)
- self.specials += [
- AsyncResetSynchronizer(self.cd_eth_tx, reset),
- AsyncResetSynchronizer(self.cd_eth_rx, reset),
- ]
-
-class GMIIPHY(Module, AutoCSR):
- def __init__(self, clock_pads, pads):
- self.dw = 8
- ###
- self.submodules.crg = GMIIPHYCRG(clock_pads, pads)
- self.submodules.tx = RenameClockDomains(GMIIPHYTX(pads), "eth_tx")
- self.submodules.rx = RenameClockDomains(GMIIPHYRX(pads), "eth_rx")
- self.sink, self.source = self.tx.sink, self.rx.source
+++ /dev/null
-from migen.fhdl.std import *
-from migen.flow.actor import Sink, Source
-from migen.bank.description import *
-from migen.genlib.record import *
-
-from misoclib.ethmac.std import *
-
-class LoopbackPHYCRG(Module, AutoCSR):
- def __init__(self):
- self._reset = CSRStorage()
- ###
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += [
- self.cd_eth_rx.clk.eq(ClockSignal()),
- self.cd_eth_tx.clk.eq(ClockSignal())
- ]
-
- reset = self._reset.storage
- self.comb += [
- self.cd_eth_rx.rst.eq(reset),
- self.cd_eth_tx.rst.eq(reset)
- ]
-
-class LoopbackPHY(Module, AutoCSR):
- def __init__(self):
- self.dw = 8
- ###
- self.submodules.crg = LoopbackPHYCRG()
- self.sink = sink = Sink(eth_description(8))
- self.source = source = Source(eth_description(8))
- self.comb += Record.connect(self.sink, self.source)
+++ /dev/null
-from migen.fhdl.std import *
-from migen.genlib.fsm import FSM, NextState
-from migen.flow.actor import Sink, Source
-from migen.bank.description import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoclib.ethmac.std import *
-
-class MIIPHYTX(Module):
- def __init__(self, pads):
- self.sink = sink = Sink(eth_description(8))
- ###
- tx_en_r = Signal()
- tx_data_r = Signal(4)
- self.sync += [
- pads.tx_er.eq(0),
- pads.tx_en.eq(tx_en_r),
- pads.tx_data.eq(tx_data_r),
- ]
-
- fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- sink.ack.eq(1),
- If(sink.stb & sink.sop,
- sink.ack.eq(0),
- NextState("SEND_LO")
- )
- )
- fsm.act("SEND_LO",
- tx_data_r.eq(sink.d[0:4]),
- tx_en_r.eq(1),
- NextState("SEND_HI")
- )
- fsm.act("SEND_HI",
- tx_data_r.eq(sink.d[4:8]),
- tx_en_r.eq(1),
- sink.ack.eq(1),
- If(sink.stb & sink.eop,
- NextState("IDLE")
- ).Else(
- NextState("SEND_LO")
- )
- )
-
-class MIIPHYRX(Module):
- def __init__(self, pads):
- self.source = source = Source(eth_description(8))
- ###
- sop = source.sop
- set_sop = Signal()
- clr_sop = Signal()
- self.sync += \
- If(clr_sop,
- sop.eq(0)
- ).Elif(set_sop,
- sop.eq(1)
- )
-
- lo = Signal(4)
- hi = Signal(4)
- load_nibble = Signal(2)
- self.sync += \
- If(load_nibble[0],
- lo.eq(pads.rx_data)
- ).Elif(load_nibble[1],
- hi.eq(pads.rx_data)
- )
- self.comb += [
- source.d.eq(Cat(lo, hi))
- ]
-
- fsm = FSM(reset_state="IDLE")
- self.submodules += fsm
- fsm.act("IDLE",
- set_sop.eq(1),
- If(pads.dv,
- load_nibble.eq(0b01),
- NextState("LOAD_HI")
- )
- )
- fsm.act("LOAD_LO",
- source.stb.eq(1),
- If(pads.dv,
- clr_sop.eq(1),
- load_nibble.eq(0b01),
- NextState("LOAD_HI")
- ).Else(
- source.eop.eq(1),
- NextState("IDLE")
- )
- )
- fsm.act("LOAD_HI",
- load_nibble.eq(0b10),
- NextState("LOAD_LO")
- )
-
-class MIIPHYCRG(Module, AutoCSR):
- def __init__(self, clock_pads, pads):
- self._reset = CSRStorage()
- ###
- self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
-
- self.clock_domains.cd_eth_rx = ClockDomain()
- self.clock_domains.cd_eth_tx = ClockDomain()
- self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
- self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
-
- reset = self._reset.storage
- self.comb += pads.rst_n.eq(~reset)
- self.specials += [
- AsyncResetSynchronizer(self.cd_eth_tx, reset),
- AsyncResetSynchronizer(self.cd_eth_rx, reset),
- ]
-
-class MIIPHY(Module, AutoCSR):
- def __init__(self, clock_pads, pads):
- self.dw = 8
- ###
- self.submodules.crg = MIIPHYCRG(clock_pads, pads)
- self.submodules.tx = RenameClockDomains(MIIPHYTX(pads), "eth_tx")
- self.submodules.rx = RenameClockDomains(MIIPHYRX(pads), "eth_rx")
- self.sink, self.source = self.tx.sink, self.rx.source
from migen.genlib.record import *
from migen.flow.actor import Sink, Source
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
class PreambleInserter(Module):
def __init__(self, d_w):
###
preamble = Signal(64, reset=eth_preamble)
- cnt_max = (64//d_w)-1
+ cnt_max = (64//d_w) - 1
cnt = Signal(max=cnt_max+1)
clr_cnt = Signal()
inc_cnt = Signal()
from migen.bank.description import *
from migen.bank.eventmanager import *
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
class SRAMWriter(Module, AutoCSR):
def __init__(self, depth, nslots=2):
###
- # packet dropped if no slot available
+ # packet dropped if no slot available
sink.ack.reset = 1
- # length computation
+ # length computation
cnt = Signal(lengthbits)
clr_cnt = Signal()
inc_cnt = Signal()
cnt.eq(cnt+inc_val)
)
- # slot computation
+ # slot computation
slot = Signal(slotbits)
inc_slot = Signal()
self.sync += \
ongoing = Signal()
discard = Signal()
- # status fifo
+ # status fifo
fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
self.submodules += fifo
- # fsm
+ # fsm
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
self._length.status.eq(fifo.dout.length),
]
- # memory
+ # memory
mems = [None]*nslots
ports = [None]*nslots
for n in range(nslots):
###
- # command fifo
+ # command fifo
fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
self.submodules += fifo
self.comb += [
self._ready.status.eq(fifo.writable)
]
- # length computation
+ # length computation
cnt = Signal(lengthbits)
clr_cnt = Signal()
inc_cnt = Signal()
cnt.eq(cnt+4)
)
- # fsm
+ # fsm
first = Signal()
last = Signal()
last_d = Signal()
NextState("IDLE")
)
- # first/last computation
+ # first/last computation
self.sync += [
If(fsm.ongoing("IDLE"),
first.eq(1)
first.eq(0)
)
]
- self.comb += last.eq(cnt+4 >= fifo.dout.length)
+ self.comb += last.eq(cnt + 4 >= fifo.dout.length)
self.sync += last_d.eq(last)
- # memory
+ # memory
rd_slot = fifo.dout.slot
mems = [None]*nslots
+++ /dev/null
-from migen.fhdl.std import *
-from migen.flow.actor import EndpointDescription
-
-eth_mtu = 1532
-eth_preamble = 0xD555555555555555
-buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
-
-def eth_description(dw):
- parameters = {
- "packetized": True
- }
- layout = [
- ("d", dw),
- ("last_be", dw//8),
- ("error", dw//8)
- ]
- return EndpointDescription(layout, parameters)
+++ /dev/null
-MSCDIR = ../../../
-PYTHON = python3
-
-CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)
-
-crc_tb:
- $(CMD) crc_tb.py
-
-preamble_tb:
- $(CMD) preamble_tb.py
-
-ethmac_tb:
- $(CMD) ethmac_tb.py
import random
+
from migen.fhdl.std import *
from migen.flow.actor import Sink, Source
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
class PacketStreamer(Module):
def __init__(self, data):
selfp.source.eop = (n == len(self.data)-1)
selfp.source.payload.d = data
yield
- while (selfp.source.ack == 0):
+ while selfp.source.ack == 0:
yield
selfp.source.stb = 0
- while (bool(random.getrandbits(1)) == 0):
+ while random.getrandbits(1):
yield
class PacketLogger(Module):
def do_simulation(self, selfp):
selfp.sink.ack = bool(random.getrandbits(1))
- if selfp.sink.stb == 1 and selfp.sink.ack:
+ if selfp.sink.stb and selfp.sink.ack:
self.data.append(selfp.sink.payload.d)
def print_results(s, l1, l2):
try:
for i, val in enumerate(l1):
if val != l2[i]:
- print(s + " : val : %02X, exp : %02X" %(val, l2[i]))
+ print(s + " : val : {:02X}, exp : {:02X}".format(val, l2[i]))
r = False
except:
r = False
from migen.fhdl.std import *
from migen.actorlib.crc import *
-from misoclib.ethmac.std import *
-
+from misoclib.ethmac.common import *
from misoclib.ethmac.test import *
frame_data = [
class TB(Module):
def __init__(self):
-
sm = self.submodules
- # Streamer (DATA) --> CRC32Inserter --> Logger (expect DATA + CRC)
+ # Streamer (DATA) --> CRC32Inserter --> Logger (expect DATA + CRC)
sm.inserter_streamer = PacketStreamer(frame_data)
sm.crc32_inserter = CRC32Inserter(eth_description(8))
sm.inserter_logger = PacketLogger()
self.crc32_inserter.source.connect(self.inserter_logger.sink),
]
- # Streamer (DATA + CRC) --> CRC32Checher --> Logger (except DATA + CRC + check)
- sm.checker_streamer = PacketStreamer(frame_data+frame_crc)
+ # Streamer (DATA + CRC) --> CRC32Checher --> Logger (except DATA + CRC + check)
+ sm.checker_streamer = PacketStreamer(frame_data + frame_crc)
sm.crc32_checker = CRC32Checker(eth_description(8))
sm.checker_logger = PacketLogger()
self.comb +=[
print_results("inserter", inserter_reference, inserter_generated)
print_results("checker", checker_reference, checker_generated)
-
if __name__ == "__main__":
from migen.sim.generic import run_simulation
run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
from migen.sim.generic import run_simulation
from misoclib.ethmac import EthMAC
-from misoclib.ethmac.phys import loopback
+from misoclib.ethmac.phy import loopback
-class WishboneMaster():
+class WishboneMaster:
def __init__(self, obj):
self.obj = obj
self.dat = 0
self.obj.stb = 0
yield
-class SRAMReaderDriver():
+class SRAMReaderDriver:
def __init__(self, obj):
self.obj = obj
def wait_done(self):
while self.obj.ev.done.pending == 0:
yield
+
def clear_done(self):
self.obj.ev.done.clear = 1
yield
length = 1500-2
- payload = [i%0xFF for i in range(length)] + [0, 0, 0, 0]
+ payload = [i % 0xFF for i in range(length)] + [0, 0, 0, 0]
errors = 0
# check rx data
for i in range(length):
- #print("%02x / %02x" %(rx_dat[i], payload[i]))
+ #print("{:02x} / {:02x}".format(rx_dat[i], payload[i]))
if rx_dat[i] != payload[i]:
errors += 1
yield
#print(selfp.ethmac.sram_reader._length.storage)
- print("Errors : %d" %errors)
+ print("Errors : {}".format(errors))
if __name__ == "__main__":
run_simulation(TB(), ncycles=16000, vcd_name="my.vcd", keep_files=True)
from migen.fhdl.std import *
-from misoclib.ethmac.std import *
+from misoclib.ethmac.common import *
from misoclib.ethmac.preamble import *
-
from misoclib.ethmac.test import *
frame_preamble = [
class TB(Module):
def __init__(self):
-
sm = self.submodules
- # Streamer (DATA) --> PreambleInserter --> Logger (expect PREAMBLE + DATA)
+ # Streamer (DATA) --> PreambleInserter --> Logger (expect PREAMBLE + DATA)
sm.inserter_streamer = PacketStreamer(frame_data)
sm.preamble_inserter = PreambleInserter(8)
sm.inserter_logger = PacketLogger()
self.preamble_inserter.source.connect(self.inserter_logger.sink),
]
- # Streamer (PREAMBLE + DATA) --> CRC32Checher --> Logger (except DATA + check)
+ # Streamer (PREAMBLE + DATA) --> CRC32Checher --> Logger (except DATA + check)
sm.checker_streamer = PacketStreamer(frame_preamble + frame_data)
sm.preamble_checker = PreambleChecker(8)
sm.checker_logger = PacketLogger()
self.preamble_checker.source.connect(self.checker_logger.sink),
]
-
def gen_simulation(self, selfp):
for i in range(500):
yield
from misoclib import lasmicon, spiflash, ethmac
from misoclib.sdramphy import k7ddrphy
from misoclib.gensoc import SDRAMSoC
-from misoclib.ethmac.phys import gmii
+from misoclib.ethmac.phy import gmii
class _CRG(Module):
def __init__(self, platform):
from misoclib import lasmicon, mxcrg, norflash16, ethmac, framebuffer, gpio
from misoclib.sdramphy import s6ddrphy
from misoclib.gensoc import SDRAMSoC
-from misoclib.ethmac.phys import mii
+from misoclib.ethmac.phy import mii
class _MXClockPads:
def __init__(self, platform):
projects / litex.git / commitdiff