i965/gen6: Declare minify(depth, level) layers for 3D stencil

Keeps following patch refactoring the table allocation
non-functional.

Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1f0a1e9a38daac13770465c65b0eddcf0ad3c6b5..fd774f42c833931f4c0439e8a6fc62827e3f8bb7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -272,7 +272,9 @@ brw_miptree_layout_gen6_hiz_stencil(struct intel_mipmap_tree *mt)
    mt->total_height = 0;
 
    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
-      intel_miptree_set_level_info(mt, level, x, y, depth);
+      intel_miptree_set_level_info(
+         mt, level, x, y,
+         mt->target == GL_TEXTURE_3D ? minify(depth, level) : depth);
 
       const unsigned img_width = ALIGN(DIV_ROUND_UP(width, bw), mt->halign);
       const unsigned img_height =