ram: Ack stores early

Stores only need a single cycle, so we can ack them early if there
isn't an older ack already in the pipeline

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index a711c3d9778e7bb3658bf80ad081b81ddf97edf4..14520b5458ab776d5af2313ceec9433ce627b2bc 100644 (file)
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -67,8 +67,16 @@ begin
                ack_buf <= '0';
                ack <= '0';
            else
-               ack <= wishbone_in.stb;
-               ack_buf <= ack;
+               -- On loads, we have a delay cycle due to BRAM bufferring
+               -- but not on stores. So try to send an early ack on a
+               -- store if we aren't behind an existing load ack.
+               --
+               if ram_we = '1' and ack = '0' then
+                   ack_buf <= '1';
+               else
+                   ack <= wishbone_in.stb;
+                   ack_buf <= ack;
+               end if;
            end if;
        end if;
     end process;