Fix handling of partial init attributes in write_verilog, fixes #997

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 9fd4ccbc8bcc6016ea13687552961efafeda4c0e..827af5d85c4061c3b7d7a5c08dbca87922d5918c 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1618,7 +1618,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
                        SigSpec sig = active_sigmap(wire);
                        Const val = wire->attributes.at("\\init");
                        for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++)
-                               active_initdata[sig[i]] = val.bits.at(i);
+                               if (val[i] == State::S0 || val[i] == State::S1)
+                                       active_initdata[sig[i]] = val[i];
                }
 
        if (!module->processes.empty())