&& i.reg_operands == i.operands - i.imm_operands
&& i.tm.opcode_modifier.vex
&& i.tm.opcode_modifier.commutative
- && (i.tm.opcode_modifier.sse2avx || optimize > 1)
+ && (i.tm.opcode_modifier.sse2avx
+ || (optimize > 1 && !i.no_optimize))
&& i.rex == REX_B
&& i.vex.register_specifier
&& !(i.vex.register_specifier->reg_flags & RegRex))
0+ <_start>:
+[a-f0-9]+: a9 7f 00 00 00 test \$0x7f,%eax
+ +[a-f0-9]+: c4 c1 61 db e4 vpand %xmm12,%xmm3,%xmm4
+ +[a-f0-9]+: c5 91 db e2 vpand %xmm2,%xmm13,%xmm4
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 fd 28 6f d1 vmovdqa64 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 7f 08 6f d1 vmovdqu8 %xmm1,%xmm2
_start:
{nooptimize} testl $0x7f, %eax
+ {nooptimize} vpand %xmm12, %xmm3, %xmm4
+ {nooptimize} vpand %xmm2, %xmm13, %xmm4
+
{nooptimize} vmovdqa32 %ymm1, %ymm2
{nooptimize} vmovdqa64 %ymm1, %ymm2
{nooptimize} vmovdqu8 %xmm1, %xmm2