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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 817c41367e37bfdcc49642f35fcdbcb8e8c13ff7..86ae3b4de7f76a98fa4d215635735e2d5a986980 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -28,7 +28,8 @@ Modes apply to Arithmetic and Logical SVP64 operations:
   *VL is altered as a result*.
 * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping for both INT
 and FP.
-* **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see [[svp64/appendix]]
+* **reduce mode**. if used correftly, a mapreduce (or a prefix sum)
+  is performed.    see [[svp64/appendix]]:
   note that there are comprehensive caveats when using this mode.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch conditional testing) and if the test fails it
 is as if the 
@@ -47,7 +48,6 @@ The Mode table for Arithmetic and Logical operations
 | --- | --- |---------|-------------------------- |
 | 00  |   0 |  dz  sz | simple mode                      |
 | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
-| 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
 | 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
 | 00  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
@@ -131,6 +131,8 @@ the appearance and effect of a Horizontal Vector Reduction. Due
 to the unusual decoupling it is also possible to perform
 prefix-sum in certain circumstances. Details are in the [[svp64/appendix]]
 
+Reduce Mode should not be confused with Parallel Reduction [[sv/remap]].
+
 # Fail-on-first
 
 Data-dependent fail-on-first has two distinct variants: one for LD/ST,