redo PO9 encoding table so that:

* bit 6 is "prefix is EXT0xx or EXT2xx
* bit 7 is "Loop-Prefixed (SVP64) or Scalar-Extended (SVP64Single)

diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn
index a34aadebd5c75896b62b66f81ee5f9e18c0334af..269e9226c3a77a5a195333845f8a6d7819b94bb9 100644 (file)
--- a/openpower/sv/po9_encoding.mdwn
+++ b/openpower/sv/po9_encoding.mdwn
@@ -78,33 +78,27 @@ The following seven new areas are defined within Primary Opcode 9 (EXT009)
 as a new 64-bit encoding space, alongside Primary Opcode 1
 (EXT1xx).
 
-| 0-5 | 6 | 7 | 8-31  | 32|33-63|Description                        |
-|-----|---|---|-------|---|-----|-----------------------------------|
-| PO9 | 0 | x | xxxx  | 0 | xxxx|  `RESERVED2` (57-bit) |
-| PO9 | 0 | 0 | !zero | 1 | DWd | SVP64Single:EXT232-263, or `RESERVED3` |
-| PO9 | 0 | 0 | 0000  | 1 | DWd | Scalar EXT232-263               |
-| PO9 | 0 | 1 | nnnn  | 1 | DWd | SVP64:EXT232-263     |
-| PO9 | 1 | 0 | 0000  | x | xxxx| `RESERVED1` (32-bit) |
-| PO9 | 1 | 0 | !zero | n | DWd | SVP64Single:EXT000-063 or `RESERVED4` |
-| PO9 | 1 | 1 | nnnn  | n | DWd | SVP64:EXT000-063       |
+|0-5| 6-29   |30 31|32-37   | 38-63  | Description      |
+|---|--------|-----|--------|--------|------------------|
+|PO9| xxxx   | x x | 010001 |  ////  | RESERVED(1)      |
+|PO9| xxxx   | x x | 000001 |  ////  | RESERVED(2)      |
+|PO9| !ZERO  | 1 1 |  !PO9  | nnnn   | SVP64Single:EXT200-263 |
+|PO9|  0000  | 1 1 |  !PO9  | nnnn   | Scalar EXT200-263  |
+|PO9|  SVRM  | 1 0 |  !PO9  | nnnn   | SVP64:EXT200-263   |
+|PO9|  0000  | 0 1 | DWd    | nnnn   | 32-bit EXT300-363  |
+|PO9| !ZERO  | 0 1 | DWd    | nnnn   | SVP64Single:EXT000-063 |
+|PO9|  SVRM  | 0 0 | DWd    | nnnn   | SVP64:EXT000-063   |
 
 Key:
 
 * **x** - a `RESERVED` encoding. Illegal Instruction Trap must be raised
-* **n** - a specification-defined value
-* **!zero** - a non-zero specification-defined value
-* **DWd** - when including bit 32 is a "Defined Word-instruction" as explained in
-  Book I Section 1.6 (Public v3.1 p11)
-
-Note that for the future SVP64Single Encoding (currently RESERVED3 and 4)
-it is prohibited to have bits 8-31 be zero, unlike for SVP64 Vector space,
-for which bits 8-31 can be zero (termed `scalar identity behaviour`). This
-prohibition allows SVP64Single to share its Encoding space with Scalar
-EXT232-263 and Scalar EXT300-363.
-
-Also that RESERVED1 and 2 are candidates for future Major opcode
-areas EXT200-231 and EXT300-363 respectively, however as RESERVED areas
-they may equally be allocated entirely differently.
+* **n** - a specification-defined value (currently `RESERVED`)
+* **!ZERO** - a non-zero specification-defined value
+* **DWd** - a "Defined Word-instruction" - Book I Section 1.6 (Public v3.1 p11)
+* **SVP64Single**: a `RESERVED` encoding
+* **SVP64**: a `RESERVED` Loop-Prefix encoding
+* **EXT200-263**: a `RESERVED` encoding for future Scalar instructions
+* **EXT300-363**: a `RESERVED` encoding for future Scalar instructions
 
 *Architectural Resource Allocation Note: Similar to ARM's `MOVPRFX`
 instruction and the original x86 REP instruction, despite "influence" over
@@ -119,8 +113,7 @@ Trap if Unvectorizable) or not be allocated at all.  This is required
 as an inviolate hard rule governing Primary Opcode 9 that may not be
 revoked under any circumstances. A useful way to think of this is that
 the Prefix Encoding is, like the 8086 REP instruction, an independent
-32-bit Defined Word-instruction. The only semi-exceptions are the Post-Increment
-Mode of LD/ST-Update and Vectorized Branch-Conditional.*
+32-bit Defined Word-instruction.*
 
 Note a particular consequence of the application of the above paragraph:
 due to the fact that the Prefix Encodings are independent, **by
@@ -134,16 +127,6 @@ apply to these two new areas** because due to the Prefixes being
 independent Defined Word-instructions the three areas are actually one and the same
 area, just as *all* Scalar Defined Word-instructions are.
 
-Encoding spaces and their potential are illustrated:
-
-| Encoding |Available bits|Scalar|Vectorizeable | SVP64Single  |PO1-Prefixable |
-|----------|--------------|------|--------------|--------------|---------------|
-|EXT000-063| 32           | yes  | yes          |yes           |yes            |
-|EXT100-163| 64           | yes  | no           |no            |not twice      |
-|RESERVED2 | 57           | N/A  |not applicable|not applicable|not applicable |
-|EXT232-263| 32           | yes  | yes          |yes           |no             |
-|RESERVED1 | 32           | N/A  | no           |no            |no             |
-
 Notes:
 
 * **PO9**-PO1 Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is
@@ -160,11 +143,6 @@ Notes:
   should not be permitted as long as it is clearly marked as Unvectorizable.
 * EXT100-163 instructions (PO1-Prefixed) are also prohibited from being
   double-PO1-prefixed (not twice prefixed)
-* RESERVED2 presently remains unallocated as of yet and therefore its
-  potential is not yet defined (Not Applicable).
-* RESERVED1 is also unallocated at present, but it is known in advance
-  that the area is Unvectorizable and also cannot be Prefixed with
-  SVP64Single.
 * Considerable care is needed both on Architectural Resource Allocation
   as well as instruction design itself. All new Scalar instructions automatically
   and inherently must be designed taking their Vectorizeable potential into