syscalls: support RISC-V architectures

diff --git a/src/openpower/syscalls/__init__.py b/src/openpower/syscalls/__init__.py
index 5888a8bce3271d7c10018521d9f8dd9b78a5e63a..c59b47a8b7c9dcda3e96890c0670f84257765ae7 100644 (file)
--- a/src/openpower/syscalls/__init__.py
+++ b/src/openpower/syscalls/__init__.py
@@ -102,11 +102,19 @@ class Dispatcher:
             yield from sysnums["ppc"]["common"].items()
             yield from sysnums["ppc"]["64"].items()
 
+        def riscv32(sysnums):
+            yield from sysnums["generic"]["arch32"].items()
+
+        def riscv64(sysnums):
+            yield from sysnums["generic"]["arch64"].items()
+
         arch = {
             "i386": i386,
             "amd64": amd64,
             "ppc": ppc,
             "ppc64": ppc64,
+            "riscv32": riscv32,
+            "riscv64": riscv64,
         }
         sysnums = table["sysnums"]
         sysargs = table["sysargs"]