xaiger: add testcase
authorEddie Hung <eddie@fpgeh.com>
Sun, 24 May 2020 15:48:23 +0000 (08:48 -0700)
committerEddie Hung <eddie@fpgeh.com>
Sun, 24 May 2020 15:48:23 +0000 (08:48 -0700)
tests/various/xaiger.ys [new file with mode: 0644]

diff --git a/tests/various/xaiger.ys b/tests/various/xaiger.ys
new file mode 100644 (file)
index 0000000..f612d2e
--- /dev/null
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input a, b, output c);
+bb #(1) bb();
+endmodule
+
+module bb(input a, b, output c);
+parameter p = 0;
+assign c = a ^ b;
+endmodule
+EOT
+blackbox bb
+hierarchy
+write_xaiger /dev/null