X86: Update the stats on the ruby x86 regressions for the new CMOVcc implementation.

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini
index 033b2dffb7daf78725cdbf3ae1777f88b35813d5..cd22dbeae203bfc9e8bd71c16bab772195546313 100644 (file)
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini
@@ -81,7 +81,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=RubyMemory
 clock=1
-config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config
+config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config
 debug=false
 debug_file=ruby.debug
 file=

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats
index 2ec29786ea0df38d2825a36dea425e902c59265a..aef340be642b2be5076a4c402d7f043a30c42649 100644 (file)
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats
@@ -2,7 +2,7 @@
 ================ Begin RubySystem Configuration Print ================
 
 RubySystem config:
-  random_seed: 30545
+  random_seed: 1234
   randomization: 0
   tech_nm: 45
   freq_mhz: 3000
@@ -14,18 +14,20 @@ DMA_Controller config: DMAController_0
   version: 0
   buffer_size: 32
   dma_sequencer: DMASequencer_0
-  number_of_TBEs: 128
+  number_of_TBEs: 256
+  recycle_latency: 10
+  request_latency: 6
   transitions_per_cycle: 32
 Directory_Controller config: DirectoryController_0
   version: 0
   buffer_size: 32
   directory_latency: 6
   directory_name: DirectoryMemory_0
+  dma_select_low_bit: 6
+  dma_select_num_bits: 0
   memory_controller_name: MemoryControl_0
-  memory_latency: 158
-  number_of_TBEs: 128
+  number_of_TBEs: 256
   recycle_latency: 10
-  to_mem_ctrl_latency: 1
   transitions_per_cycle: 32
 L1Cache_Controller config: L1CacheController_0
   version: 0
@@ -33,7 +35,8 @@ L1Cache_Controller config: L1CacheController_0
   cache: l1u_0
   cache_response_latency: 12
   issue_latency: 2
-  number_of_TBEs: 128
+  number_of_TBEs: 256
+  recycle_latency: 10
   sequencer: Sequencer_0
   transitions_per_cycle: 32
 Cache config: l1u_0
@@ -103,80 +106,40 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jul/06/2009 11:11:42
+Real time: Aug/09/2009 03:58:51
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.28
-Virtual_time_in_minutes: 0.00466667
-Virtual_time_in_hours:   7.77778e-05
-Virtual_time_in_days:    7.77778e-05
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours:   9.44444e-05
+Virtual_time_in_days:    3.93519e-06
 
-Ruby_current_time: 5491501
+Ruby_current_time: 5504001
 Ruby_start_time: 1
-Ruby_cycles: 5491500
+Ruby_cycles: 5504000
 
-mbytes_resident: 144.855
-mbytes_total: 1330.54
-resident_ratio: 0.108873
+mbytes_resident: 144.359
+mbytes_total: 1352.23
+resident_ratio: 0.106763
 
 Total_misses: 0
 total_misses: 0 [ 0 ]
 user_misses: 0 [ 0 ]
 supervisor_misses: 0 [ 0 ]
 
-instruction_executed: 1 [ 1 ]
-ruby_cycles_executed: 5491501 [ 5491501 ]
-cycles_per_instruction: 5.4915e+06 [ 5.4915e+06 ]
-misses_per_thousand_instructions: 0 [ 0 ]
+ruby_cycles_executed: 5504001 [ 5504001 ]
 
 transactions_started: 0 [ 0 ]
 transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
 cycles_per_transaction: 0 [ 0 ]
 misses_per_transaction: 0 [ 0 ]
 
-L1D_cache cache stats: 
-  L1D_cache_total_misses: 0
-  L1D_cache_total_demand_misses: 0
-  L1D_cache_total_prefetches: 0
-  L1D_cache_total_sw_prefetches: 0
-  L1D_cache_total_hw_prefetches: 0
-  L1D_cache_misses_per_transaction: 0
-  L1D_cache_misses_per_instruction: 0
-  L1D_cache_instructions_per_misses: NaN
-
-  L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats: 
-  L1I_cache_total_misses: 0
-  L1I_cache_total_demand_misses: 0
-  L1I_cache_total_prefetches: 0
-  L1I_cache_total_sw_prefetches: 0
-  L1I_cache_total_hw_prefetches: 0
-  L1I_cache_misses_per_transaction: 0
-  L1I_cache_misses_per_instruction: 0
-  L1I_cache_instructions_per_misses: NaN
-
-  L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats: 
-  L2_cache_total_misses: 0
-  L2_cache_total_demand_misses: 0
-  L2_cache_total_prefetches: 0
-  L2_cache_total_sw_prefetches: 0
-  L2_cache_total_hw_prefetches: 0
-  L2_cache_misses_per_transaction: 0
-  L2_cache_misses_per_instruction: 0
-  L2_cache_instructions_per_misses: NaN
-
-  L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -185,27 +148,16 @@ DMA-0:0
 
 Busy Bank Count:0
 
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
 prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
 Request vs. RubySystem State Profile
 --------------------------------
 
@@ -228,11 +180,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 37781
-page_faults: 0
+page_reclaims: 38267
+page_faults: 1
 swaps: 0
 block_inputs: 0
-block_outputs: 40
+block_outputs: 0
 
 Network Stats
 -------------
@@ -266,7 +218,17 @@ links_utilized_percent_switch_3: 0
   links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
 
 
- --- DMA ---
+l1u_0 cache stats: 
+  l1u_0_total_misses: 0
+  l1u_0_total_demand_misses: 0
+  l1u_0_total_prefetches: 0
+  l1u_0_total_sw_prefetches: 0
+  l1u_0_total_hw_prefetches: 0
+  l1u_0_misses_per_transaction: nan
+
+  l1u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+ --- DMA 0 ---
  - Event Counts -
 ReadRequest  0
 WriteRequest  0
@@ -281,7 +243,7 @@ BUSY_RD  Data  0 <--
 
 BUSY_WR  Ack  0 <-- 
 
- --- Directory ---
+ --- Directory 0 ---
  - Event Counts -
 GETX  0
 GETS  0
@@ -344,7 +306,7 @@ ID_W  DMA_READ  0 <--
 ID_W  DMA_WRITE  0 <-- 
 ID_W  Memory_Ack  0 <-- 
 
- --- L1Cache ---
+ --- L1Cache 0 ---
  - Event Counts -
 Load  0
 Ifetch  0

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr
index 5af43697b8c969f531f2b5ae0376174a1d48d706..dba65c3fcfffe3fcb1fea19e1a3eb27d22f5d519 100755 (executable)
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr
@@ -1,23 +1,7 @@
 ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
+Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
+Solution: Re-compile with RUBY_DEBUG set to true.
 print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout
index 90ac86d82b7836d0adba2c002582a4b3e6dbad58..85200a1c81a2c1709edfe0ad148b9e88723110c4 100755 (executable)
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout
@@ -5,13 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:09:41
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:11:41
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby
+M5 compiled Aug  9 2009 03:58:47
+M5 revision 33faa9915d16 6486 default tip
+M5 started Aug  9 2009 03:58:49
+M5 executing on tater
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby
 Global frequency set at 1000000000000 ticks per second
-  Debug: Adding to filter: 'q' (Queue)
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 5491500 because target called exit()
+Exiting @ tick 5504000 because target called exit()

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt
index 6fed8184dbd1bac1cd8a4272ed3cd65ddc030d24..e8b0be97bd0022919685bbba81ecf27ab398dc51 100644 (file)
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt
@@ -1,17 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  70231                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1362472                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
-host_tick_rate                               40570791                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   7886                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1384684                       # Number of bytes of host memory used
+host_seconds                                     1.21                       # Real time elapsed on the host
+host_tick_rate                                4559114                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        9494                       # Number of instructions simulated
-sim_seconds                                  0.000005                       # Number of seconds simulated
-sim_ticks                                     5491500                       # Number of ticks simulated
+sim_insts                                        9519                       # Number of instructions simulated
+sim_seconds                                  0.000006                       # Number of seconds simulated
+sim_ticks                                     5504000                       # Number of ticks simulated
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            10984                       # number of cpu cycles simulated
-system.cpu.num_insts                             9494                       # Number of instructions executed
+system.cpu.numCycles                            11009                       # number of cpu cycles simulated
+system.cpu.num_insts                             9519                       # Number of instructions executed
 system.cpu.num_refs                              1987                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 70c54a02f049189ceb6e88921138189d389193a7..bb30a84581ee6b8ea63a0fce4177d0a249dda5e8 100644 (file)
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -78,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=RubyMemory
 clock=1
-config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config
+config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config
 debug=false
 debug_file=ruby.debug
 file=

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 68f2b9852064258d94f93aa56b9d553ca2cb842b..7d6d1b1870719d48fbcd4e37e99ed86a943605af 100644 (file)
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -2,7 +2,7 @@
 ================ Begin RubySystem Configuration Print ================
 
 RubySystem config:
-  random_seed: 184716
+  random_seed: 1234
   randomization: 0
   tech_nm: 45
   freq_mhz: 3000
@@ -14,18 +14,20 @@ DMA_Controller config: DMAController_0
   version: 0
   buffer_size: 32
   dma_sequencer: DMASequencer_0
-  number_of_TBEs: 128
+  number_of_TBEs: 256
+  recycle_latency: 10
+  request_latency: 6
   transitions_per_cycle: 32
 Directory_Controller config: DirectoryController_0
   version: 0
   buffer_size: 32
   directory_latency: 6
   directory_name: DirectoryMemory_0
+  dma_select_low_bit: 6
+  dma_select_num_bits: 0
   memory_controller_name: MemoryControl_0
-  memory_latency: 158
-  number_of_TBEs: 128
+  number_of_TBEs: 256
   recycle_latency: 10
-  to_mem_ctrl_latency: 1
   transitions_per_cycle: 32
 L1Cache_Controller config: L1CacheController_0
   version: 0
@@ -33,7 +35,8 @@ L1Cache_Controller config: L1CacheController_0
   cache: l1u_0
   cache_response_latency: 12
   issue_latency: 2
-  number_of_TBEs: 128
+  number_of_TBEs: 256
+  recycle_latency: 10
   sequencer: Sequencer_0
   transitions_per_cycle: 32
 Cache config: l1u_0
@@ -103,82 +106,42 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jul/06/2009 11:11:44
+Real time: Aug/09/2009 04:00:22
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 4
+Elapsed_time_in_minutes: 0.0666667
+Elapsed_time_in_hours: 0.00111111
+Elapsed_time_in_days: 4.62963e-05
 
-Virtual_time_in_seconds: 0.87
-Virtual_time_in_minutes: 0.0145
-Virtual_time_in_hours:   0.000241667
-Virtual_time_in_days:    0.000241667
+Virtual_time_in_seconds: 1.19
+Virtual_time_in_minutes: 0.0198333
+Virtual_time_in_hours:   0.000330556
+Virtual_time_in_days:    1.37731e-05
 
 Ruby_current_time: 26617001
 Ruby_start_time: 1
 Ruby_cycles: 26617000
 
-mbytes_resident: 145.273
-mbytes_total: 1330.63
-resident_ratio: 0.109179
+mbytes_resident: 144.777
+mbytes_total: 1352.41
+resident_ratio: 0.107057
 
 Total_misses: 0
 total_misses: 0 [ 0 ]
 user_misses: 0 [ 0 ]
 supervisor_misses: 0 [ 0 ]
 
-instruction_executed: 1 [ 1 ]
 ruby_cycles_executed: 26617001 [ 26617001 ]
-cycles_per_instruction: 2.6617e+07 [ 2.6617e+07 ]
-misses_per_thousand_instructions: 0 [ 0 ]
 
 transactions_started: 0 [ 0 ]
 transactions_ended: 0 [ 0 ]
-instructions_per_transaction: 0 [ 0 ]
 cycles_per_transaction: 0 [ 0 ]
 misses_per_transaction: 0 [ 0 ]
 
-L1D_cache cache stats: 
-  L1D_cache_total_misses: 0
-  L1D_cache_total_demand_misses: 0
-  L1D_cache_total_prefetches: 0
-  L1D_cache_total_sw_prefetches: 0
-  L1D_cache_total_hw_prefetches: 0
-  L1D_cache_misses_per_transaction: 0
-  L1D_cache_misses_per_instruction: 0
-  L1D_cache_instructions_per_misses: NaN
-
-  L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats: 
-  L1I_cache_total_misses: 0
-  L1I_cache_total_demand_misses: 0
-  L1I_cache_total_prefetches: 0
-  L1I_cache_total_sw_prefetches: 0
-  L1I_cache_total_hw_prefetches: 0
-  L1I_cache_misses_per_transaction: 0
-  L1I_cache_misses_per_instruction: 0
-  L1I_cache_instructions_per_misses: NaN
-
-  L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats: 
-  L2_cache_total_misses: 0
-  L2_cache_total_demand_misses: 0
-  L2_cache_total_prefetches: 0
-  L2_cache_total_sw_prefetches: 0
-  L2_cache_total_hw_prefetches: 0
-  L2_cache_misses_per_transaction: 0
-  L2_cache_misses_per_instruction: 0
-  L2_cache_instructions_per_misses: NaN
-
-  L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Memory control:
+
+Memory control MemoryControl_0:
   memory_total_requests: 1082
   memory_reads: 557
   memory_writes: 525
@@ -205,30 +168,19 @@ DMA-0:0
 
 Busy Bank Count:0
 
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 1 count: 1082 average: 0.485213 | standard deviation: 0.500693 | 557 525 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8873 average:     1 | standard deviation: 0 | 0 8873 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 2 max: 279 count: 8873 average: 12.5938 | standard deviation: 41.1326 | 0 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_1: [binsize: 2 max: 279 count: 6886 average: 9.86669 | standard deviation: 35.7801 | 0 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_2: [binsize: 2 max: 279 count: 1053 average: 24.4786 | standard deviation: 57.8541 | 0 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_3: [binsize: 2 max: 259 count: 934 average: 19.3009 | standard deviation: 51.067 | 0 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency: [binsize: 2 max: 277 count: 8873 average: 11.531 | standard deviation: 40.8912 | 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 277 count: 6886 average: 8.82021 | standard deviation: 35.5704 | 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 277 count: 1053 average: 23.3457 | standard deviation: 57.517 | 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 257 count: 934 average: 18.197 | standard deviation: 50.763 | 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
 prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
 Request vs. RubySystem State Profile
 --------------------------------
 
@@ -249,13 +201,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1082 average:     0 | standa
 Resource Usage
 --------------
 page_size: 4096
-user_time: 0
+user_time: 1
 system_time: 0
-page_reclaims: 37883
+page_reclaims: 38363
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 48
+block_outputs: 0
 
 Network Stats
 -------------
@@ -301,7 +253,22 @@ links_utilized_percent_switch_3: 0.000135502
   outgoing_messages_switch_3_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
 
- --- DMA ---
+l1u_0 cache stats: 
+  l1u_0_total_misses: 557
+  l1u_0_total_demand_misses: 557
+  l1u_0_total_prefetches: 0
+  l1u_0_total_sw_prefetches: 0
+  l1u_0_total_hw_prefetches: 0
+  l1u_0_misses_per_transaction: inf
+
+  l1u_0_request_type_LD:   25.1346%
+  l1u_0_request_type_ST:   17.4147%
+  l1u_0_request_type_IFETCH:   57.4506%
+
+  l1u_0_access_mode_type_SupervisorMode:   557    100%
+  l1u_0_request_size: [binsize: log2 max: 8 count: 557 average: 7.5368 | standard deviation: 1.45496 | 0 12 1 42 502 ]
+
+ --- DMA 0 ---
  - Event Counts -
 ReadRequest  0
 WriteRequest  0
@@ -316,7 +283,7 @@ BUSY_RD  Data  0 <--
 
 BUSY_WR  Ack  0 <-- 
 
- --- Directory ---
+ --- Directory 0 ---
  - Event Counts -
 GETX  557
 GETS  0
@@ -379,7 +346,7 @@ ID_W  DMA_READ  0 <--
 ID_W  DMA_WRITE  0 <-- 
 ID_W  Memory_Ack  0 <-- 
 
- --- L1Cache ---
+ --- L1Cache 0 ---
  - Event Counts -
 Load  1053
 Ifetch  6886

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
index 5af43697b8c969f531f2b5ae0376174a1d48d706..dba65c3fcfffe3fcb1fea19e1a3eb27d22f5d519 100755 (executable)
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
@@ -1,23 +1,7 @@
 ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
+Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
+Solution: Re-compile with RUBY_DEBUG set to true.
 print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
 warn: instruction 'fnstcw_Mw' unimplemented

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
index f24cd70ebc4fe039ad4e624de8f15ff0434d6876..e450b1234d4bdab90bc8e0c27c60d208b3f23d1f 100755 (executable)
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -5,13 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jul  6 2009 11:09:41
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:11:43
-M5 executing on maize
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
+M5 compiled Aug  9 2009 04:00:16
+M5 revision 33faa9915d16+ 6486+ default tip
+M5 started Aug  9 2009 04:00:18
+M5 executing on tater
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000000 ticks per second
-  Debug: Adding to filter: 'q' (Queue)
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
 Exiting @ tick 26617000 because target called exit()

diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 65a218a7ce743c7d0a2e6a0d94dbb391965faede..f970da10113009da8e5316038b52982e160c1d07 100644 (file)
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -1,17 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  12919                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1362572                       # Number of bytes of host memory used
-host_seconds                                     0.74                       # Real time elapsed on the host
-host_tick_rate                               36211191                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   2962                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1384872                       # Number of bytes of host memory used
+host_seconds                                     3.21                       # Real time elapsed on the host
+host_tick_rate                                8282962                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                        9494                       # Number of instructions simulated
+sim_insts                                        9519                       # Number of instructions simulated
 sim_seconds                                  0.000027                       # Number of seconds simulated
 sim_ticks                                    26617000                       # Number of ticks simulated
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            53234                       # number of cpu cycles simulated
-system.cpu.num_insts                             9494                       # Number of instructions executed
+system.cpu.num_insts                             9519                       # Number of instructions executed
 system.cpu.num_refs                              1987                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls