+2018-04-09 Andrey Belevantsev <abel@ispras.ru>
+
+ PR rtl-optimization/83530
+
+ * sel-sched.c (force_next_insn): New global variable.
+ (remove_insn_for_debug): When force_next_insn is true, also leave only
+ next insn in the ready list.
+ (sel_sched_region): When the region wasn't scheduled, make another pass
+ over it with force_next_insn set to 1.
+
2018-04-08 Monk Chiang <sh.chiang04@gmail.com>
* config.gcc (nds32le-*-*, nds32be-*-*): Add nds32/nds32_intrinsic.h
distinguishing between bookkeeping copies and original insns. */
static int max_uid_before_move_op = 0;
+/* When true, we're always scheduling next insn on the already scheduled code
+ to get the right insn data for the following bundling or other passes. */
+static int force_next_insn = 0;
+
/* Remove from AV_VLIW_P all instructions but next when debug counter
tells us so. Next instruction is fetched from BNDS. */
static void
remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
{
- if (! dbg_cnt (sel_sched_insn_cnt))
+ if (! dbg_cnt (sel_sched_insn_cnt) || force_next_insn)
/* Leave only the next insn in av_vliw. */
{
av_set_iterator av_it;
if (schedule_p)
sel_sched_region_1 ();
else
- /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
- reset_sched_cycles_p = true;
-
+ {
+ /* Schedule always selecting the next insn to make the correct data
+ for bundling or other later passes. */
+ pipelining_p = false;
+ force_next_insn = 1;
+ sel_sched_region_1 ();
+ force_next_insn = 0;
+ }
+ reset_sched_cycles_p = pipelining_p;
sel_region_finish (reset_sched_cycles_p);
}
+2018-04-09 Andrey Belevantsev <abel@ispras.ru>
+
+ PR rtl-optimization/83530
+ * gcc.dg/pr83530.c: New test.
+
2018-04-07 Thomas Koenig <tkoenig@gcc.gnu.org>
PR middle-end/82976
--- /dev/null
+/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -fmodulo-sched -fselective-scheduling2" } */
+int vm, z0;
+short int mz;
+
+int
+ny (void)
+{
+ int ch;
+
+ for (ch = 0; ch < 6; ++ch)
+ vm += ch / vm;
+
+ return z0 + mz;
+}