# Authors: Gabe Black
microcode = '''
-def macroop MOVAPS_R_M {
+def macroop MOVAPS_XMM_M {
# Check low address.
ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
ldfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVAPS_R_P {
+def macroop MOVAPS_XMM_P {
rdip t7
# Check low address.
ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
ldfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVAPS_M_R {
+def macroop MOVAPS_M_XMM {
# Check low address.
stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVAPS_P_R {
+def macroop MOVAPS_P_XMM {
rdip t7
# Check low address.
stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
stfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVAPS_R_R {
+def macroop MOVAPS_XMM_XMM {
# Check low address.
movfp xmml, xmmlm, dataSize=8
movfp xmmh, xmmhm, dataSize=8
# MOVHPD
# MOVLPS
-def macroop MOVLPD_R_M {
+def macroop MOVLPD_XMM_M {
ldfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVLPD_R_P {
+def macroop MOVLPD_XMM_P {
rdip t7
ldfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVLPD_M_R {
+def macroop MOVLPD_M_XMM {
stfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVLPD_P_R {
+def macroop MOVLPD_P_XMM {
rdip t7
stfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVLPD_R_R {
+def macroop MOVLPD_XMM_XMM {
movfp xmml, xmmlm, dataSize=8
};
# MOVLHPS
# MOVSS
-def macroop MOVSD_R_M {
+def macroop MOVSD_XMM_M {
# Zero xmmh
ldfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVSD_R_P {
+def macroop MOVSD_XMM_P {
rdip t7
# Zero xmmh
ldfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVSD_M_R {
+def macroop MOVSD_M_XMM {
stfp xmml, seg, sib, disp, dataSize=8
};
-def macroop MOVSD_P_R {
+def macroop MOVSD_P_XMM {
rdip t7
stfp xmml, seg, riprel, disp, dataSize=8
};
-def macroop MOVSD_R_R {
+def macroop MOVSD_XMM_XMM {
movfp xmml, xmmlm, dataSize=8
};
'''
env.addReg(ModRMRegIndex)
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % ModRMRegIndex)
- Name += "_R"
+ if opType.tag == "P":
+ Name += "_MMX"
+ elif opType.tag == "V":
+ Name += "_XMM"
+ else:
+ Name += "_R"
elif opType.tag in ("E", "Q", "W"):
# This might refer to memory or to a register. We need to
# divide it up farther.
# modrm addressing.
memEnv = copy.copy(env)
memEnv.doModRM = True
+ regSuffix = "_R"
+ if opType.tag == "Q":
+ regSuffix = "_MMX"
+ elif opType.tag == "W":
+ regSuffix = "_XMM"
return doSplitDecode("MODRM_MOD",
- {"3" : (specializeInst, Name + "_R", copy.copy(opTypes), regEnv)},
- (doRipRelativeDecode, Name, copy.copy(opTypes), memEnv))
+ {"3" : (specializeInst, Name + regSuffix,
+ copy.copy(opTypes), regEnv)},
+ (doRipRelativeDecode, Name,
+ copy.copy(opTypes), memEnv))
elif opType.tag in ("I", "J"):
# Immediates
env.addToDisassembly(
env.addReg(ModRMRMIndex)
env.addToDisassembly(
"printReg(out, %s, regSize);\n" % ModRMRMIndex)
- Name += "_R"
+ if opType.tag == "PR":
+ Name += "_MMX"
+ elif opType.tag == "VR":
+ Name += "_XMM"
+ else:
+ Name += "_R"
elif opType.tag in ("X", "Y"):
# This type of memory addressing is for string instructions.
# They'll use the right index and segment internally.