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diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 071349985cb95cb83a5c0a16e6b9dcc30c29be51..56ca9e91a9a27a9e7b4693a2ba243bde446d1def 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -53,6 +53,8 @@ As mentioned above, OE=1 is not applicable in SV, freeing this bit for alternati
 
 This leaves several Major Opcodes free for use by SV to fit alternative instructions: Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST operations, and others critical to an efficient, effective 3D GPU and VPU ISA, and included as standard in other commercially-successful GPU ISAs.
 
+Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions.
+
 # Register Naming and size
 
 SV Registers are simply the INT, FP and CR register files extended